New mechanism to define SRAM/memory map with automatic bounds checking

This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.

The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).

BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.

Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614
Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213370
Reviewed-on: http://review.coreboot.org/9283
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: Aaron Durbin <adurbin@google.com>

8 files changed, 59 insertions, 84 deletions

diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig
index 24bf8649a0..c87698a8d2 100644
--- a/src/soc/nvidia/tegra132/Kconfig
+++ b/src/soc/nvidia/tegra132/Kconfig
@@ -43,50 +43,6 @@ config CBFS_ROM_OFFSET
 	hex "offset of CBFS data in ROM"
 	default 0x40080
 
-config BOOTBLOCK_BASE
-	hex
-	default 0x40020000
-
-config ROMSTAGE_BASE
-	hex
-	default 0x40025000
-
-config SYS_SDRAM_BASE
-	hex
-	default 0x80000000
-
-config RAMSTAGE_BASE
-	hex
-	default 0x80200000
-
-config BOOTBLOCK_STACK_TOP
-	hex
-	default 0x40020000
-
-config BOOTBLOCK_STACK_BOTTOM
-	hex
-	default 0x4001c000
-
-config ROMSTAGE_STACK_TOP
-	hex
-	default 0x40020000
-
-config ROMSTAGE_STACK_BOTTOM
-	hex
-	default 0x4001c000
-
-config CBFS_CACHE_ADDRESS
-	hex "memory address to put CBFS cache data"
-	default 0x40006000
-
-config CBFS_CACHE_SIZE
-	hex "size of CBFS cache data"
-	default 0x00016000
-
-config CONSOLE_PRERAM_BUFFER_BASE
-	hex "memory address of the CBMEM console buffer"
-	default 0x40004020
-
 config MTS_DIRECTORY
 	string "Directory where MTS microcode files are located"
 	default "3rdparty/cpu/nvidia/tegra132/current/prod"
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 10d4d4e5f0..81d08f54df 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -114,7 +114,7 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN) $(CBOOTIMAGE)
 	echo "Bctcopy    = 1;" >> $(BCT_WRAPPER)
 	echo "Bctfile    = $(BCT_BIN);" >> $(BCT_WRAPPER)
 	echo "MtsPreboot = $(PREBOOT_MTS_FILE),0x4000f000,0x4000f000,Complete;" >> $(BCT_WRAPPER)
-	echo "BootLoader = $<,$(CONFIG_BOOTBLOCK_BASE),$(CONFIG_BOOTBLOCK_BASE),Complete;" >> $(BCT_WRAPPER)
+	echo "BootLoader = $<,$(call loadaddr,bootblock),$(call loadaddr,bootblock),Complete;" >> $(BCT_WRAPPER)
 	@printf "    CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
 	$(CBOOTIMAGE) $(CBOOTIMAGE_OPTS) $(BCT_WRAPPER) $@
 
diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c
index a18e1b86dc..bd644d4c5c 100644
--- a/src/soc/nvidia/tegra132/addressmap.c
+++ b/src/soc/nvidia/tegra132/addressmap.c
@@ -23,6 +23,7 @@
 #include <console/console.h>
 #include <soc/addressmap.h>
 #include <soc/id.h>
+#include <symbols.h>
 #include "mc.h"
 #include "sdram.h"
 
@@ -105,7 +106,7 @@ static void memory_in_range(uintptr_t *base_mib, uintptr_t *end_mib,
 	uintptr_t end;
 	int i;
 
-	base = CONFIG_SYS_SDRAM_BASE / MiB;
+	base = (uintptr_t)_dram / MiB;
 	end = base + sdram_size_mb();
 
 	/* Requested limits out of range. */
diff --git a/src/soc/nvidia/tegra132/bootblock_asm.S b/src/soc/nvidia/tegra132/bootblock_asm.S
index 1b2fbb7709..bf63c02433 100644
--- a/src/soc/nvidia/tegra132/bootblock_asm.S
+++ b/src/soc/nvidia/tegra132/bootblock_asm.S
@@ -42,17 +42,5 @@ ENTRY(_start)
 	 */
 	msr	cpsr_cxf, #0xdf
 
-	stack_init stack=.Stack size=.Stack_size seed=1 func=main
+	stack_init stack_top=_estack stack_bottom=_stack seed=1 func=main
 ENDPROC(_start)
-
-/* we do it this way because it's a 32-bit constant and
- * in some cases too far away to be loaded as just an offset
- * from IP
- */
-.align 2
-.Stack:
-	.word CONFIG_BOOTBLOCK_STACK_TOP
-.align 2
-/* create this size the same way we do in ramstage.ld: top-bottom */
-.Stack_size:
-	.word CONFIG_BOOTBLOCK_STACK_TOP - CONFIG_BOOTBLOCK_STACK_BOTTOM
diff --git a/src/soc/nvidia/tegra132/cbfs.c b/src/soc/nvidia/tegra132/cbfs.c
index 7b75f7c8c1..648d13663a 100644
--- a/src/soc/nvidia/tegra132/cbfs.c
+++ b/src/soc/nvidia/tegra132/cbfs.c
@@ -19,12 +19,12 @@
 
 
 #include <cbfs.h>  /* This driver serves as a CBFS media source. */
+#include <symbols.h>
 
 #include "spi.h"
 
 int init_default_cbfs_media(struct cbfs_media *media)
 {
 	return initialize_tegra_spi_cbfs_media(media,
-		(void*)CONFIG_CBFS_CACHE_ADDRESS,
-		CONFIG_CBFS_CACHE_SIZE);
+		_cbfs_cache, _cbfs_cache_size);
 }
diff --git a/src/soc/nvidia/tegra132/memlayout.ld b/src/soc/nvidia/tegra132/memlayout.ld
new file mode 100644
index 0000000000..63cf4f031c
--- /dev/null
+++ b/src/soc/nvidia/tegra132/memlayout.ld
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/*
+ * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
+ * so the bootblock loading address must be placed after that. After the
+ * handoff that area may be reclaimed for other uses, e.g. CBFS cache.
+ * TODO: Did this change on Tegra132? What's the new valid range?
+ */
+
+SECTIONS
+{
+	SRAM_START(0x40000000)
+	/* 16K hole */
+	PRERAM_CBMEM_CONSOLE(0x40004000, 8K)
+	CBFS_CACHE(0x40006000, 88K)
+	STACK(0x4001C000, 16K)
+	BOOTBLOCK(0x40020000, 20K)
+	ROMSTAGE(0x40025000, 108K)
+	SRAM_END(0x40040000)
+
+	DRAM_START(0x80000000)
+	RAMSTAGE(0x80200000, 192K)
+}
diff --git a/src/soc/nvidia/tegra132/romstage_asm.S b/src/soc/nvidia/tegra132/romstage_asm.S
index ac3c93ebc1..d0b036cbd6 100644
--- a/src/soc/nvidia/tegra132/romstage_asm.S
+++ b/src/soc/nvidia/tegra132/romstage_asm.S
@@ -23,17 +23,5 @@
         .section ".text", "ax", %progbits
 
 ENTRY(main)
-	stack_init stack=.Stack size=.Stack_size seed=0 func=romstage
+	stack_init stack_top=_estack stack_bottom=_stack seed=0 func=romstage
 ENDPROC(main)
-
-/* we do it this way because it's a 32-bit constant and
- * in some cases too far away to be loaded as just an offset
- * from IP
- */
-.align 2
-.Stack:
-	.word CONFIG_ROMSTAGE_STACK_TOP
-.align 2
-.Stack_size:
-	.word CONFIG_ROMSTAGE_STACK_TOP - CONFIG_ROMSTAGE_STACK_BOTTOM
-
diff --git a/src/soc/nvidia/tegra132/stack.S b/src/soc/nvidia/tegra132/stack.S
index 6d3cd4e446..3b877e4be6 100644
--- a/src/soc/nvidia/tegra132/stack.S
+++ b/src/soc/nvidia/tegra132/stack.S
@@ -19,21 +19,19 @@
 
 /* Macro to initialize stack, perform seeding if required and finally call the
  * function provided
- * @stack : Stack address
- * @size  : Stack size
- * @seed  : Stack seeding required (1=yes/otherwise=no)
- * @func  : Function to call after initializing stack
+ * @stack_top    : First address above the stack
+ * @stack_bottom : Lowest address on the stack
+ * @seed         : Stack seeding required (1=yes/otherwise=no)
+ * @func         : Function to call after initializing stack
  */
-.macro stack_init stack, size, seed, func
+.macro stack_init stack_top, stack_bottom, seed, func
         /* Check if stack seeding is required */
 	mov	r0, #\seed
 	cmp     r0, #1
 	bne     call_func
 	/* Stack seeding */
-	ldr     r0, \stack
-	ldr	r1, \size
-	sub	r0, r0, r1
-	ldr	r1, \stack
+	ldr     r0, =\stack_bottom
+	ldr	r1, =\stack_top
 	ldr	r2, =0xdeadbeef
 init_stack_loop:
 	str	r2, [r0]
@@ -42,6 +40,6 @@ init_stack_loop:
 	bne	init_stack_loop
 
 call_func:
-	ldr	sp, \stack /* Set up stack pointer */
+	ldr	sp, =\stack_top /* Set up stack pointer */
 	bl	\func
 .endm