diff options
| author | Tom Warren <twarren@nvidia.com> | 2014-10-09 16:01:33 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2015-04-04 15:03:55 +0200 |
| commit | 834d2b98dea3eb976b41a988d053278d88ce541d (patch) | |
| tree | 0ad817f247044cdc4c3a73a637fc2c9799a923e1 /src/soc/nvidia/tegra132 | |
| parent | acbf32a0422555b5edfaa60559dbcaf90adb4167 (diff) | |
tegra132: Store ODMDATA from BCT into PMC scratch for use by kernel
In able to do earlyprintk spew on LP0 resume, the kernel needs to
know the board UART. ODMDATA (in bct/odmdata.cfg) contains this info,
and the kernel looks for it in PMC_SCRATCH20. Fetch the ODMDATA word
from the BCT copy stored in IRAM by the BootROM.
BUG=chrome-os-partner:32015
BRANCH=none
TEST=Built for Rush and Ryu OK. Dumped PMC_SCRATCH20 in TegraShell
on Rush and confirmed value is what's in odmdata.cfg.
Original-Change-Id: I63f33558ee8b00bd6c1e313efcd531e1d5fc67eb
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/222402
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 3f6a21afdb81f7d2ae90119c563535b4c87c9ade)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I9819ffdf0f7618f0dd8dc50f81b5b26d6f94bfbd
Reviewed-on: http://review.coreboot.org/9257
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132')
| -rw-r--r-- | src/soc/nvidia/tegra132/bootblock.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index 6481eb3e4d..6f2505011b 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -29,6 +29,29 @@ #include "power.h" +#define BCT_OFFSET_IN_BIT 0x50 +#define ODMDATA_OFFSET_IN_BCT 0x6A8 +#define TEGRA_SRAM_MAX (TEGRA_SRAM_BASE + TEGRA_SRAM_SIZE) + +static void save_odmdata(void) +{ + struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; + uintptr_t bct_offset; + u32 odmdata; + + // pmc.odmdata: [18:19]: console type, [15:17]: UART id. + // TODO(twarren) ODMDATA is stored in the BCT, from bct/odmdata.cfg. + // I use the BCT offset in the BIT in SRAM to locate the BCT, and + // pick up the ODMDATA word at BCT offset 0x6A8. I could use a BCT + // struct header from cbootimage, but it seems like overkill for this. + + bct_offset = read32((void *)(TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT)); + if (bct_offset > TEGRA_SRAM_BASE && bct_offset < TEGRA_SRAM_MAX) { + odmdata = read32((void *)(bct_offset + ODMDATA_OFFSET_IN_BCT)); + write32(odmdata, &pmc->odmdata); + } +} + void __attribute__((weak)) bootblock_mainboard_early_init(void) { /* Empty default implementation. */ @@ -52,6 +75,9 @@ void main(void) CLK_H_APBDMA, 0, CLK_V_MSELECT, 0, 0); + /* Find ODMDATA in IRAM and save it to scratch reg */ + save_odmdata(); + bootblock_mainboard_early_init(); if (CONFIG_BOOTBLOCK_CONSOLE) { |