diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-06-25 15:19:13 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-04 18:16:27 +0100 |
| commit | b68cb9e8ae63d734f5cea42d54eef11d726a5964 (patch) | |
| tree | a4df873c04b8a2cb49d3d67be032ac1631eb7904 /src/soc/nvidia/tegra132 | |
| parent | f0d150e0bad67a6ffd6fb175ed1591f944df106e (diff) | |
coreboot t132: Enable loading of romstage from CBFS media
Add proper Kconfig options and initialize cbfs media to enable loading of
romstage
BUG=None
BRANCH=None
TEST=Compiles successfully for rush and cbfs_load_stage returns entry pointer
for romstage
Original-Change-Id: If62edcdc0496d89d30003ffd7b827b77835910fd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205762
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c89c05bc86fd6c1e49fbed5e0730659b64bffc6c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I68c10171424c85605b5065a19634d3c5dd639b78
Reviewed-on: http://review.coreboot.org/8572
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc/nvidia/tegra132')
| -rw-r--r-- | src/soc/nvidia/tegra132/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/bootblock.c | 14 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/cbfs.c | 6 |
3 files changed, 26 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 23f7c6e7f2..4dc71fe2c5 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -54,4 +54,12 @@ config STACK_BOTTOM hex default 0x4001c000 +config CBFS_CACHE_ADDRESS + hex "memory address to put CBFS cache data" + default 0x40006000 + +config CBFS_CACHE_SIZE + hex "size of CBFS cache data" + default 0x00016000 + endif diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index 46b7b3ab56..62e5228829 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -24,12 +24,15 @@ #include <console/console.h> #include <soc/clock.h> #include <soc/nvidia/tegra/apbmisc.h> +#include <arch/stages.h> #include "pinmux.h" #include "power.h" void main(void) { + void *entry; + // enable pinmux clamp inputs clamp_tristate_inputs(); @@ -65,5 +68,14 @@ void main(void) printk(BIOS_INFO, "T132 bootblock: Mainboard bootblock init done\n"); - while(1); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); + + if (entry) { + printk(BIOS_INFO, "T132 bootblock: jumping to romstage\n"); + stage_exit(entry); + } else { + printk(BIOS_INFO, "T132 bootblock: fallback/romstage not found\n"); + } + + hlt(); } diff --git a/src/soc/nvidia/tegra132/cbfs.c b/src/soc/nvidia/tegra132/cbfs.c index ac4a5570e6..7b75f7c8c1 100644 --- a/src/soc/nvidia/tegra132/cbfs.c +++ b/src/soc/nvidia/tegra132/cbfs.c @@ -20,7 +20,11 @@ #include <cbfs.h> /* This driver serves as a CBFS media source. */ +#include "spi.h" + int init_default_cbfs_media(struct cbfs_media *media) { - return 0; + return initialize_tegra_spi_cbfs_media(media, + (void*)CONFIG_CBFS_CACHE_ADDRESS, + CONFIG_CBFS_CACHE_SIZE); } |