diff options
| author | Jimmy Zhang <jimmzhang@nvidia.com> | 2014-11-14 21:12:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-10 20:43:02 +0200 |
| commit | 11e9622fc0a2c62ceb37124e33a0942a20141510 (patch) | |
| tree | 16e3a01676ac0e8dde35c07b3c0ac31d9667de75 /src/soc/nvidia/tegra132 | |
| parent | 0ee0d92978955db636d7fb9b763f959c8aa413a8 (diff) | |
tegra132: Add panel mode spec
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: I23dae7bfdeb8e33a6ea5c9de0fb953a7c4d31345
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6cac26deeea0e024f2f6bd1850a41894f801bc5f
Original-Change-Id: Ie77f8df4ba3425e0dd4e4243dd38157480de0efb
Original-Reviewed-on: https://chromium-review.googlesource.com/229913
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9515
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132')
| -rw-r--r-- | src/soc/nvidia/tegra132/chip.h | 35 |
1 files changed, 34 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra132/chip.h b/src/soc/nvidia/tegra132/chip.h index f2936dde6c..23f2cd8f38 100644 --- a/src/soc/nvidia/tegra132/chip.h +++ b/src/soc/nvidia/tegra132/chip.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. + * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,6 +29,39 @@ struct soc_nvidia_tegra132_config { /* Address to monitor if spintable employed. */ uintptr_t spintable_addr; + + /* + * panel default specification + */ + u32 xres; /* the width of H display active area */ + u32 yres; /* the height of V display active area */ + u32 framebuffer_bits_per_pixel; + u32 color_depth; /* color format */ + + u64 display_controller; /* dc block base address */ + u32 framebuffer_base; + + /* + * Technically, we can compute this. At the same time, some platforms + * might want to specify a specific size for their own reasons. If it + * is zero the soc code will compute it as + * xres*yres*framebuffer_bits_per_pixel/8 + */ + u32 framebuffer_size; + + int href_to_sync; /* HSYNC position with respect to line start */ + int hsync_width; /* the width of HSYNC pulses */ + int hback_porch; /* the distance between HSYNC trailing edge to + beginning of H display active area */ + int hfront_porch; /* the distance between end of H display active + area to the leading edge of HSYNC */ + int vref_to_sync; + int vsync_width; + int vback_porch; + int vfront_porch; + int refresh; /* display refresh rate */ + + int pixel_clock; /* dc pixel clock source rate */ }; #endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */ |