src/soc: Capitalize CPU, ACPI, RAM and ROM

Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15963
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>

6 files changed, 8 insertions, 8 deletions

diff --git a/src/soc/nvidia/tegra132/bootblock_asm.S b/src/soc/nvidia/tegra132/bootblock_asm.S
index 857900a6eb..62554422db 100644
--- a/src/soc/nvidia/tegra132/bootblock_asm.S
+++ b/src/soc/nvidia/tegra132/bootblock_asm.S
@@ -30,7 +30,7 @@
 
 ENTRY(_start)
 	/*
-	 * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
+	 * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
 	 * aborts may happen early and crash before the abort handlers are
 	 * installed, but at least the problem will show up near the code that
 	 * causes it.
diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
index 5a307b57bb..95f91d8f8d 100644
--- a/src/soc/nvidia/tegra132/ccplex.c
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -133,14 +133,14 @@ static void request_ram_repair(void)
 
 	stopwatch_init(&sw);
 
-	/* Perform cluster 0 ram repair */
+	/* Perform cluster 0 RAM repair */
 	reg = read32(&flow->ram_repair);
 	reg |= req;
 	write32(&flow->ram_repair, reg);
 	while ((read32(&flow->ram_repair) & sts) != sts)
 		;
 
-	/* Perform cluster 1 ram repair */
+	/* Perform cluster 1 RAM repair */
 	reg = read32(&flow->ram_repair_cluster1);
 	reg |= req;
 	write32(&flow->ram_repair_cluster1, reg);
diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c
index 0db120d8d2..be12b856b1 100644
--- a/src/soc/nvidia/tegra132/clock.c
+++ b/src/soc/nvidia/tegra132/clock.c
@@ -508,7 +508,7 @@ void clock_cpu0_config(void)
 		/* wait and try again */
 		if (timeout >= CLK_SWITCH_TIMEOUT_US) {
 			printk(BIOS_ERR, "%s: PLLX programming timeout. "
-				"Switching cpu clock has falied.\n",
+				"Switching CPU clock has falied.\n",
 				__func__);
 			break;
 		}
diff --git a/src/soc/nvidia/tegra132/include/soc/sdram_param.h b/src/soc/nvidia/tegra132/include/soc/sdram_param.h
index 6bc5aeaf49..ce85058383 100644
--- a/src/soc/nvidia/tegra132/include/soc/sdram_param.h
+++ b/src/soc/nvidia/tegra132/include/soc/sdram_param.h
@@ -794,9 +794,9 @@ struct sdram_params {
 	/* Set if bit 6 select is greater than bit 7 select; uses aremc.
 	   spec packet SWIZZLE_BIT6_GT_BIT7 */
 	uint32_t SwizzleRankByteEncode;
-	/* Specifies enable and offset for patched boot rom write */
+	/* Specifies enable and offset for patched boot ROM write */
 	uint32_t BootRomPatchControl;
-	/* Specifies data for patched boot rom write */
+	/* Specifies data for patched boot ROM write */
 	uint32_t BootRomPatchData;
 	/* Specifies the value for MC_MTS_CARVEOUT_BOM */
 	uint32_t McMtsCarveoutBom;
diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
index 94d22634a4..bd4e5c4218 100644
--- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
@@ -645,7 +645,7 @@ void lp0_resume(void)
 
 	power_on_main_cpu();
 
-	// Perform ram repair after cpu is powered on.
+	// Perform RAM repair after CPU is powered on.
 	ram_repair();
 
 	clear_cpu_resets();
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index 3b45aff63d..c5c1392c07 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -72,7 +72,7 @@ void romstage(void)
 	cbmem_initialize_empty();
 
 	ccplex_cpu_prepare();
-	printk(BIOS_INFO, "T132 romstage: cpu prepare done\n");
+	printk(BIOS_INFO, "T132 romstage: CPU prepare done\n");
 
 	ccplex_load_mts();
 	printk(BIOS_INFO, "T132 romstage: MTS loading done\n");