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authorJulius Werner <jwerner@chromium.org>2015-02-19 14:51:15 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:22:28 +0200
commit2f37bd65518865688b9234afce0d467508d6f465 (patch)
treeeba5ed799de966299602b30c70d51dd40eaadd73 /src/soc/nvidia/tegra132/padconfig.c
parent1f60f971fc89ef841e81b978964b38278d597b1d (diff)
arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132/padconfig.c')
-rw-r--r--src/soc/nvidia/tegra132/padconfig.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/nvidia/tegra132/padconfig.c b/src/soc/nvidia/tegra132/padconfig.c
index 790f10f9c0..46cf944441 100644
--- a/src/soc/nvidia/tegra132/padconfig.c
+++ b/src/soc/nvidia/tegra132/padconfig.c
@@ -36,7 +36,7 @@ static inline uint32_t pad_get_pinmux(int index)
static inline void pad_set_pinmux(int index, uint32_t reg)
{
- return writel(reg, &pinmux_regs[index]);
+ return write32(&pinmux_regs[index], reg);
}
static inline void pad_set_gpio_out(int gpio_index, int val)
@@ -45,10 +45,10 @@ static inline void pad_set_gpio_out(int gpio_index, int val)
int port = gpio_index_to_port(gpio_index);
int bit = gpio_to_bit(gpio_index);
- writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit),
- &regs->out_value_mask[port]);
- writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit),
- &regs->out_enable_mask[port]);
+ write32(&regs->out_value_mask[port],
+ (1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit));
+ write32(&regs->out_enable_mask[port],
+ (1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit));
}
static inline void pad_set_mode(int gpio_index, int sfio_or_gpio)
@@ -57,8 +57,8 @@ static inline void pad_set_mode(int gpio_index, int sfio_or_gpio)
int port = gpio_index_to_port(gpio_index);
int bit = gpio_to_bit(gpio_index);
- writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit),
- &regs->config_mask[port]);
+ write32(&regs->config_mask[port],
+ (1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit));
}
static inline void pad_set_gpio_mode(int gpio_index)