arm(64): Globally replace writel(v, a) with write32(a, v)

This patch is a raw application of the following spatch to src/:

@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 40 insertions, 39 deletions

diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
index 29fb9dedd6..8392a58228 100644
--- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
@@ -261,17 +261,17 @@ inline static void write32(uint32_t val, void *addr)
 
 inline static void setbits32(uint32_t bits, void *addr)
 {
-	writel(read32(addr) | bits, addr);
+	write32(addr, read32(addr) | bits);
 }
 
 inline static void clrbits32(uint32_t bits, void *addr)
 {
-	writel(read32(addr) & ~bits, addr);
+	write32(addr, read32(addr) & ~bits);
 }
 
 static void __attribute__((noreturn)) reset(void)
 {
-	writel(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
+	write32(clk_rst_rst_devices_l_ptr, SWR_TRIG_SYS_RST);
 	halt();
 }
 
@@ -370,18 +370,18 @@ static void enable_uart(void)
 	clrbits32(uart_mask, uart_rst_reg);
 
 	/* Program UART clock source: PLLP (408000000) */
-	writel(0, uart_clk_source);
+	write32(uart_clk_source, 0);
 
 	/* Program 115200n8 to the uart port */
 	/* baud-rate of 115200 */
-	writel(LCR_DLAB, (uart_base + UART_LCR));
-	writel((UART_RATE_115200 & 0xff), (uart_base + UART_THR_DLAB));
-	writel((UART_RATE_115200 >> 8), (uart_base + UART_IER_DLAB));
+	write32((uart_base + UART_LCR), LCR_DLAB);
+	write32((uart_base + UART_THR_DLAB), (UART_RATE_115200 & 0xff));
+	write32((uart_base + UART_IER_DLAB), (UART_RATE_115200 >> 8));
 	/* 8-bit and no parity */
-	writel(LCR_WD_SIZE_8, (uart_base + UART_LCR));
+	write32((uart_base + UART_LCR), LCR_WD_SIZE_8);
 	/* enable and clear RX/TX FIFO */
-	writel((FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO),
-	       (uart_base + UART_IIR_FCR));
+	write32((uart_base + UART_IIR_FCR),
+		(FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO));
 }
 
 /* Accessors. */
@@ -401,7 +401,7 @@ static unsigned get_osc_freq(void)
 
 static void enable_jtag(void)
 {
-	writel(PP_CONFIG_CTL_JTAG, misc_pp_config_ctl_ptr);
+	write32(misc_pp_config_ctl_ptr, PP_CONFIG_CTL_JTAG);
 }
 
 /* Clock configuration. */
@@ -417,7 +417,7 @@ static void config_oscillator(void)
 	osc_ctrl &= ~OSC_XOFS_MASK;
 	osc_ctrl |= (xofs << OSC_XOFS_SHIFT);
 	osc_ctrl |= OSC_XOE;
-	writel(osc_ctrl, clk_rst_osc_ctrl_ptr);
+	write32(clk_rst_osc_ctrl_ptr, osc_ctrl);
 }
 
 static void config_pllu(void)
@@ -462,24 +462,24 @@ static void config_pllu(void)
 	// Configure PLLU.
 	uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE |
 			(divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT);
-	writel(base, clk_rst_pllu_base_ptr);
+	write32(clk_rst_pllu_base_ptr, base);
 	uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) |
 			(lfcon << PLLU_LFCON_SHIFT);
-	writel(misc, clk_rst_pllu_misc_ptr);
+	write32(clk_rst_pllu_misc_ptr, misc);
 
 	// Enable PLLU.
 	base &= ~PLLU_BYPASS;
 	base |= PLLU_ENABLE;
-	writel(base, clk_rst_pllu_base_ptr);
+	write32(clk_rst_pllu_base_ptr, base);
 	misc |= PLLU_LOCK_ENABLE;
-	writel(misc, clk_rst_pllu_misc_ptr);
+	write32(clk_rst_pllu_misc_ptr, misc);
 }
 
 static void enable_cpu_clocks(void)
 {
 	// Enable the CPU complex clock.
-	writel(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
-	writel(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
+	write32(clk_rst_clk_enb_l_set_ptr, CLK_ENB_CPU);
+	write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP);
 }
 
 
@@ -489,7 +489,7 @@ static void enable_cpu_clocks(void)
 static void config_core_sight(void)
 {
 	// Enable the CoreSight clock.
-	writel(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
+	write32(clk_rst_clk_out_enb_u_set_ptr, CLK_ENB_CSITE);
 
 	/*
 	 * De-assert CoreSight reset.
@@ -497,7 +497,7 @@ static void config_core_sight(void)
 	 *       now. It will be restored to its original clock source
 	 *       when the CPU-side restoration code runs.
 	 */
-	writel(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
+	write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST);
 }
 
 
@@ -508,11 +508,11 @@ static void clear_cpu_resets(void)
 	/* Hold CPU1 in reset */
 	setbits32(SET_CXRESET1, clk_rst_rst_cpulp_cmplx_set_ptr);
 
-	writel(CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG,
-	       clk_rst_rst_cpug_cmplx_clr_ptr);
+	write32(clk_rst_rst_cpug_cmplx_clr_ptr,
+		CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG);
 
-	writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
-	       clk_rst_rst_cpug_cmplx_clr_ptr);
+	write32(clk_rst_rst_cpug_cmplx_clr_ptr,
+		CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0);
 }
 
 
@@ -542,7 +542,8 @@ static void power_on_partition(unsigned id)
 	uint32_t bit = 0x1 << id;
 	if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) {
 		// Partition is not on. Turn it on.
-		writel(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
+		write32(pmc_ctlr_pwrgate_toggle_ptr,
+			id | PWRGATE_TOGGLE_START);
 
 		// Wait until the partition is powerd on.
 		while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit))
@@ -572,15 +573,15 @@ static void power_on_main_cpu(void)
 	 */
 	uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr);
 
-	writel(orig_timer * (204000000 / 32768),
-	       pmc_ctlr_cpupwrgood_timer_ptr);
+	write32(pmc_ctlr_cpupwrgood_timer_ptr,
+		orig_timer * (204000000 / 32768));
 
 	power_on_partition(PARTID_CRAIL);
 	power_on_partition(PARTID_C0NC);
 	power_on_partition(PARTID_CE0);
 
 	// Restore the original PMC_CPUPWRGOOD_TIMER.
-	writel(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
+	write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer);
 }
 
 
@@ -609,7 +610,7 @@ void lp0_resume(void)
 	config_oscillator();
 
 	// Program SUPER_CCLK_DIVIDER.
-	writel(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
+	write32(clk_rst_super_cclk_div_ptr, SUPER_CDIV_ENB);
 
 	config_core_sight();
 
@@ -623,12 +624,12 @@ void lp0_resume(void)
 	 * T132 always resets to AARCH32 and SW needs to write RMR_EL3
 	 * to bootstrap into AARCH64.
 	 */
-	writel(get_wakeup_vector(), pmc_ctlr_secure_scratch34_ptr);
-	writel(0, pmc_ctlr_secure_scratch35_ptr);
-	writel((uint32_t)aarch64_trampoline, evp_cpu_reset_ptr);
+	write32(pmc_ctlr_secure_scratch34_ptr, get_wakeup_vector());
+	write32(pmc_ctlr_secure_scratch35_ptr, 0);
+	write32(evp_cpu_reset_ptr, (uint32_t)aarch64_trampoline);
 
 	// Select CPU complex clock source.
-	writel(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
+	write32(clk_rst_cclk_burst_policy_ptr, CCLK_PLLP_BURST_POLICY);
 
 	// Disable PLLX since it isn't used as CPU clock source.
 	clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr);
@@ -637,12 +638,12 @@ void lp0_resume(void)
 	uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr);
 	ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK;
 	ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT;
-	writel(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
+	write32(clk_rst_cpu_softrst_ctrl2_ptr, ack_width);
 
 	// Disable VPR.
-	writel(0, mc_video_protect_size_mb_ptr);
-	writel(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
-               mc_video_protect_reg_ctrl_ptr);
+	write32(mc_video_protect_size_mb_ptr, 0);
+	write32(mc_video_protect_reg_ctrl_ptr,
+		VIDEO_PROTECT_WRITE_ACCESS_DISABLE);
 
 	enable_cpu_clocks();
 
@@ -655,8 +656,8 @@ void lp0_resume(void)
 
 	// Halt the AVP.
 	while (1)
-		writel(FLOW_MODE_STOP | EVENT_JTAG,
-		       flow_ctlr_halt_cop_events_ptr);
+		write32(flow_ctlr_halt_cop_events_ptr,
+		        FLOW_MODE_STOP | EVENT_JTAG);
 }