diff options
| author | Julius Werner <jwerner@chromium.org> | 2014-10-20 13:25:21 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-08 09:26:14 +0200 |
| commit | 96195eeb71545b070e37413bfad1520ceca3da54 (patch) | |
| tree | 4de9b88caa9bb4fd0150aed5df1cee89a82a2a52 /src/soc/nvidia/tegra132/include | |
| parent | dae15a63e426230117b575f9acc504110748e98f (diff) | |
tegra132: Change all SoC headers to <soc/headername.h> system
This patch aligns tegra132 to the new SoC header include scheme.
Also alphabetized headers in affected files since we touch them anyway.
BUG=None
TEST=Tested with whole series. Compiled Rush_Ryu.
Change-Id: I5cdf4008a65db84f15c937ef53aab5e4d3ef24c4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5c5c63d7b6399d3eb8a211b15d47829fe93a591
Original-Change-Id: Ifafd4d42d4fb04a1c37e8a5f23877c2b550cf44c
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224505
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9369
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132/include')
22 files changed, 3218 insertions, 6 deletions
diff --git a/src/soc/nvidia/tegra132/include/soc/ccplex.h b/src/soc/nvidia/tegra132/include/soc/ccplex.h new file mode 100644 index 0000000000..bd0679b259 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/ccplex.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_CCPLEX_H__ +#define __SOC_NVIDIA_TEGRA132_CCPLEX_H__ + +#include <stdint.h> + +#define MTS_LOAD_ADDRESS 0x82000000 + +/* Prepare the clocks and rails to start the cpu. */ +void ccplex_cpu_prepare(void); + +/* Loads the MTS microcode. Return 0 on success, < 0 on error. */ +int ccplex_load_mts(void); + +/* Start cpu0 and have it start executing at entry_addr */ +void ccplex_cpu_start(void *entry_addr); + +#endif /* __SOC_NVIDIA_TEGRA132_CCPLEX_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/clk_rst.h b/src/soc/nvidia/tegra132/include/soc/clk_rst.h new file mode 100644 index 0000000000..bde2b56fd3 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/clk_rst.h @@ -0,0 +1,561 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA132_CLK_RST_H_ +#define _TEGRA132_CLK_RST_H_ +#include <stdint.h> +#include <stddef.h> + +/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ +struct __attribute__ ((__packed__)) clk_rst_ctlr { + u32 rst_src; /* _RST_SOURCE, 0x000 */ + u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */ + u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */ + u32 rst_dev_u; /* _RST_DEVICES_U, 0x00c */ + u32 clk_out_enb_l; /* _CLK_OUT_ENB_L, 0x010 */ + u32 clk_out_enb_h; /* _CLK_OUT_ENB_H, 0x014 */ + u32 clk_out_enb_u; /* _CLK_OUT_ENB_U, 0x018 */ + u32 _rsv0; /* 0x01c */ + u32 cclk_brst_pol; /* _CCLK_BURST_POLICY, 0x020 */ + u32 super_cclk_div; /* _SUPER_CCLK_DIVIDER, 0x024 */ + u32 sclk_brst_pol; /* _SCLK_BURST_POLICY, 0x028 */ + u32 super_sclk_div; /* _SUPER_SCLK_DIVIDER, 0x02C */ + u32 clk_sys_rate; /* _CLK_SYSTEM_RATE, 0x030 */ + u32 _rsv1[3]; /* 0x034-03c */ + u32 cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY, 0x040 */ + u32 clk_mask_arm; /* _CLK_MASK_ARM, 0x044 */ + u32 misc_clk_enb; /* _MISC_CLK_ENB, 0x048 */ + u32 clk_cpu_cmplx; /* _CLK_CPU_CMPLX, 0x04C */ + u32 osc_ctrl; /* _OSC_CTRL, 0x050 */ + u32 pll_lfsr; /* _PLL_LFSR, 0x054 */ + u32 osc_freq_det; /* _OSC_FREQ_DET, 0x058 */ + u32 osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS, 0x05C */ + u32 _rsv2[8]; /* 0x060-07C */ + u32 pllc_base; /* _PLLC_BASE, 0x080 */ + u32 pllc_out; /* _PLLC_OUT, 0x084 */ + u32 pllc_misc2; /* _PLLC_MISC2, 0x088 */ + u32 pllc_misc; /* _PLLC_MISC, 0x08c */ + u32 pllm_base; /* _PLLM_BASE, 0x090 */ + u32 pllm_out; /* _PLLM_OUT, 0x094 */ + u32 pllm_misc1; /* _PLLM_MISC1, 0x098 */ + u32 pllm_misc2; /* _PLLM_MISC2, 0x09c */ + u32 pllp_base; /* _PLLP_BASE, 0x0a0 */ + u32 pllp_outa; /* _PLLP_OUTA, 0x0a4 */ + u32 pllp_outb; /* _PLLP_OUTB, 0x0a8 */ + u32 pllp_misc; /* _PLLP_MISC, 0x0ac */ + u32 plla_base; /* _PLLA_BASE, 0x0b0 */ + u32 plla_out; /* _PLLA_OUT, 0x0b4 */ + u32 _rsv3; /* 0x0b8 */ + u32 plla_misc; /* _PLLA_MISC, 0x0bc */ + u32 pllu_base; /* _PLLU_BASE, 0x0c0 */ + u32 _rsv4[2]; /* 0x0c4-0c8 */ + u32 pllu_misc; /* _PLLU_MISC, 0x0cc */ + u32 plld_base; /* _PLLD_BASE, 0x0d0 */ + u32 _rsv5[2]; /* 0x0d4-0d8 */ + u32 plld_misc; /* _PLLD_MISC, 0x0dc */ + u32 pllx_base; /* _PLLX_BASE, 0x0e0 */ + u32 pllx_misc; /* _PLLX_MISC, 0x0e4 */ + u32 plle_base; /* _PLLE_BASE, 0x0e8 */ + u32 plle_misc; /* _PLLE_MISC, 0x0ec */ + u32 plls_base; /* _PLLS_BASE, 0x0f0 */ + u32 plls_misc; /* _PLLS_MISC, 0x0f4 */ + u32 _rsv6[2]; /* 0x0f8-0fc */ + u32 clk_src_i2s1; /* _CLK_SOURCE_I2S1, 0x100 */ + u32 clk_src_i2s2; /* _CLK_SOURCE_I2S2, 0x104 */ + u32 clk_src_spdif_out; /* _CLK_SOURCE_SPDIF_OUT, 0x108 */ + u32 clk_src_spdif_in; /* _CLK_SOURCE_SPDIF_IN, 0x10c */ + u32 clk_src_pwm; /* _CLK_SOURCE_PWM, 0x110 */ + u32 _rsv7; /* 0x114 */ + u32 clk_src_sbc2; /* _CLK_SOURCE_SBC2, 0x118 */ + u32 clk_src_sbc3; /* _CLK_SOURCE_SBC3, 0x11c */ + u32 _rsv8; /* 0x120 */ + u32 clk_src_i2c1; /* _CLK_SOURCE_I2C1, 0x124 */ + u32 clk_src_i2c5; /* _CLK_SOURCE_I2C5, 0x128 */ + u32 _rsv9[2]; /* 0x12c-130 */ + u32 clk_src_sbc1; /* _CLK_SOURCE_SBC1, 0x134 */ + u32 clk_src_disp1; /* _CLK_SOURCE_DISP1, 0x138 */ + u32 clk_src_disp2; /* _CLK_SOURCE_DISP2, 0x13c */ + u32 _rsv10[2]; /* 0x140-144 */ + u32 clk_src_vi; /* _CLK_SOURCE_VI, 0x148 */ + u32 _rsv11; /* 0x14c */ + u32 clk_src_sdmmc1; /* _CLK_SOURCE_SDMMC1, 0x150 */ + u32 clk_src_sdmmc2; /* _CLK_SOURCE_SDMMC2, 0x154 */ + u32 clk_src_g3d; /* _CLK_SOURCE_G3D, 0x158 */ + u32 clk_src_g2d; /* _CLK_SOURCE_G2D, 0x15c */ + u32 clk_src_ndflash; /* _CLK_SOURCE_NDFLASH, 0x160 */ + u32 clk_src_sdmmc4; /* _CLK_SOURCE_SDMMC4, 0x164 */ + u32 clk_src_vfir; /* _CLK_SOURCE_VFIR, 0x168 */ + u32 clk_src_epp; /* _CLK_SOURCE_EPP, 0x16c */ + u32 clk_src_mpe; /* _CLK_SOURCE_MPE, 0x170 */ + u32 clk_src_hsi; /* _CLK_SOURCE_HSI, 0x174 */ + u32 clk_src_uarta; /* _CLK_SOURCE_UARTA, 0x178 */ + u32 clk_src_uartb; /* _CLK_SOURCE_UARTB, 0x17c */ + u32 clk_src_host1x; /* _CLK_SOURCE_HOST1X, 0x180 */ + u32 _rsv12[2]; /* 0x184-188 */ + u32 clk_src_hdmi; /* _CLK_SOURCE_HDMI, 0x18c */ + u32 _rsv13[2]; /* 0x190-194 */ + u32 clk_src_i2c2; /* _CLK_SOURCE_I2C2, 0x198 */ + u32 clk_src_emc; /* _CLK_SOURCE_EMC, 0x19c */ + u32 clk_src_uartc; /* _CLK_SOURCE_UARTC, 0x1a0 */ + u32 _rsv14; /* 0x1a4 */ + u32 clk_src_vi_sensor; /* _CLK_SOURCE_VI_SENSOR, 0x1a8 */ + u32 _rsv15[2]; /* 0x1ac-1b0 */ + u32 clk_src_sbc4; /* _CLK_SOURCE_SBC4, 0x1b4 */ + u32 clk_src_i2c3; /* _CLK_SOURCE_I2C3, 0x1b8 */ + u32 clk_src_sdmmc3; /* _CLK_SOURCE_SDMMC3, 0x1bc */ + u32 clk_src_uartd; /* _CLK_SOURCE_UARTD, 0x1c0 */ + u32 clk_src_uarte; /* _CLK_SOURCE_UARTE, 0x1c4 */ + u32 clk_src_vde; /* _CLK_SOURCE_VDE, 0x1c8 */ + u32 clk_src_owr; /* _CLK_SOURCE_OWR, 0x1cc */ + u32 clk_src_nor; /* _CLK_SOURCE_NOR, 0x1d0 */ + u32 clk_src_csite; /* _CLK_SOURCE_CSITE, 0x1d4 */ + u32 clk_src_i2s0; /* _CLK_SOURCE_I2S0, 0x1d8 */ + u32 clk_src_dtv; /* _CLK_SOURCE_DTV, 0x1dc */ + u32 _rsv16[4]; /* 0x1e0-1ec */ + u32 clk_src_msenc; /* _CLK_SOURCE_MSENC, 0x1f0 */ + u32 clk_src_tsec; /* _CLK_SOURCE_TSEC, 0x1f4 */ + u32 _rsv17; /* 0x1f8 */ + u32 clk_src_osc; /* _CLK_SOURCE_OSC, 0x1fc */ + u32 _rsv18[32]; /* 0x200-27c */ + u32 clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ + u32 clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ + u32 clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ + u32 rst_dev_x; /* _RST_DEVICES_X_0, 0x28c */ + u32 rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ + u32 rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ + u32 _rsv19[23]; /* 0x298-2f0 */ + u32 dfll_base; /* _DFLL_BASE_0, 0x2f4 */ + u32 _rsv20[2]; /* 0x2f8-2fc */ + u32 rst_dev_l_set; /* _RST_DEV_L_SET 0x300 */ + u32 rst_dev_l_clr; /* _RST_DEV_L_CLR 0x304 */ + u32 rst_dev_h_set; /* _RST_DEV_H_SET 0x308 */ + u32 rst_dev_h_clr; /* _RST_DEV_H_CLR 0x30c */ + u32 rst_dev_u_set; /* _RST_DEV_U_SET 0x310 */ + u32 rst_dev_u_clr; /* _RST_DEV_U_CLR 0x314 */ + u32 _rsv21[2]; /* 0x318-31c */ + u32 clk_enb_l_set; /* _CLK_ENB_L_SET 0x320 */ + u32 clk_enb_l_clr; /* _CLK_ENB_L_CLR 0x324 */ + u32 clk_enb_h_set; /* _CLK_ENB_H_SET 0x328 */ + u32 clk_enb_h_clr; /* _CLK_ENB_H_CLR 0x32c */ + u32 clk_enb_u_set; /* _CLK_ENB_U_SET 0x330 */ + u32 clk_enb_u_clr; /* _CLK_ENB_U_CLR 0x334 */ + u32 _rsv22; /* 0x338 */ + u32 ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD, 0x33c */ + u32 rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET, 0x340 */ + u32 rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR, 0x344 */ + u32 clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET, 0x348 */ + u32 clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET, 0x34c */ + u32 _rsv23[2]; /* 0x350-354 */ + u32 rst_dev_v; /* _RST_DEVICES_V, 0x358 */ + u32 rst_dev_w; /* _RST_DEVICES_W, 0x35c */ + u32 clk_out_enb_v; /* _CLK_OUT_ENB_V, 0x360 */ + u32 clk_out_enb_w; /* _CLK_OUT_ENB_W, 0x364 */ + u32 cclkg_brst_pol; /* _CCLKG_BURST_POLICY, 0x368 */ + u32 super_cclkg_div; /* _SUPER_CCLKG_DIVIDER, 0x36c */ + u32 cclklp_brst_pol; /* _CCLKLP_BURST_POLICY, 0x370 */ + u32 super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER, 0x374 */ + u32 clk_cpug_cmplx; /* _CLK_CPUG_CMPLX, 0x378 */ + u32 clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX, 0x37c */ + u32 cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL, 0x380 */ + u32 cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1, 0x384 */ + u32 cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2, 0x388 */ + u32 _rsv24[9]; /* 0x38c-3ac */ + u32 clk_src_g3d2; /* _CLK_SOURCE_G3D2, 0x3b0 */ + u32 clk_src_mselect; /* _CLK_SOURCE_MSELECT, 0x3b4 */ + u32 clk_src_tsensor; /* _CLK_SOURCE_TSENSOR, 0x3b8 */ + u32 clk_src_i2s3; /* _CLK_SOURCE_I2S3, 0x3bc */ + u32 clk_src_i2s4; /* _CLK_SOURCE_I2S4, 0x3c0 */ + u32 clk_src_i2c4; /* _CLK_SOURCE_I2C4, 0x3c4 */ + u32 clk_src_sbc5; /* _CLK_SOURCE_SBC5, 0x3c8 */ + u32 clk_src_sbc6; /* _CLK_SOURCE_SBC6, 0x3cc */ + u32 clk_src_audio; /* _CLK_SOURCE_AUDIO, 0x3d0 */ + u32 _rsv25; /* 0x3d4 */ + u32 clk_src_dam0; /* _CLK_SOURCE_DAM0, 0x3d8 */ + u32 clk_src_dam1; /* _CLK_SOURCE_DAM1, 0x3dc */ + u32 clk_src_dam2; /* _CLK_SOURCE_DAM2, 0x3e0 */ + u32 clk_src_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X,0x3e4 */ + u32 clk_src_actmon; /* _CLK_SOURCE_ACTMON, 0x3e8 */ + u32 clk_src_extperiph1; /* _CLK_SOURCE_EXTPERIPH1, 0x3ec */ + u32 clk_src_extperiph2; /* _CLK_SOURCE_EXTPERIPH2, 0x3f0 */ + u32 clk_src_extperiph3; /* _CLK_SOURCE_EXTPERIPH3, 0x3f4 */ + u32 clk_src_nand_speed; /* _CLK_SOURCE_NAND_SPEED, 0x3f8 */ + u32 clk_src_i2c_slow; /* _CLK_SOURCE_I2C_SLOW, 0x3fc */ + u32 clk_src_sys; /* _CLK_SOURCE_SYS, 0x400 */ + u32 _rsv26[4]; /* 0x404-410 */ + u32 clk_src_sor; /* _CLK_SOURCE_SOR_0, 0x414 */ + u32 _rsv261[2]; /* 0x404-410 */ + u32 clk_src_sata_oob; /* _CLK_SOURCE_SATA_OOB, 0x420 */ + u32 clk_src_sata; /* _CLK_SOURCE_SATA, 0x424 */ + u32 clk_src_hda; /* _CLK_SOURCE_HDA, 0x428 */ + u32 _rsv27; /* 0x42c */ + u32 rst_dev_v_set; /* _RST_DEV_V_SET, 0x430 */ + u32 rst_dev_v_clr; /* _RST_DEV_V_CLR, 0x434 */ + u32 rst_dev_w_set; /* _RST_DEV_W_SET, 0x438 */ + u32 rst_dev_w_clr; /* _RST_DEV_W_CLR, 0x43c */ + u32 clk_enb_v_set; /* _CLK_ENB_V_SET, 0x440 */ + u32 clk_enb_v_clr; /* _CLK_ENB_V_CLR, 0x444 */ + u32 clk_enb_w_set; /* _CLK_ENB_W_SET, 0x448 */ + u32 clk_enb_w_clr; /* _CLK_ENB_W_CLR, 0x44c */ + u32 rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET, 0x450 */ + u32 rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR, 0x454 */ + u32 rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET, 0x458 */ + u32 rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR, 0x45C */ + u32 clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET, 0x460 */ + u32 clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR, 0x464 */ + u32 clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET, 0x468 */ + u32 clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR, 0x46c */ + u32 cpu_cmplx_status; /* _CPU_CMPLX_STATUS, 0x470 */ + u32 _rsv28; /* 0x474 */ + u32 intstatus; /* _INTSTATUS, 0x478 */ + u32 intmask; /* _INTMASK, 0x47c */ + u32 utmip_pll_cfg0; /* _UTMIP_PLL_CFG0, 0x480 */ + u32 utmip_pll_cfg1; /* _UTMIP_PLL_CFG1, 0x484 */ + u32 utmip_pll_cfg2; /* _UTMIP_PLL_CFG2, 0x488 */ + u32 plle_aux; /* _PLLE_AUX, 0x48c */ + u32 sata_pll_cfg0; /* _SATA_PLL_CFG0, 0x490 */ + u32 sata_pll_cfg1; /* _SATA_PLL_CFG1, 0x494 */ + u32 pcie_pll_cfg0; /* _PCIE_PLL_CFG0, 0x498 */ + u32 prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK, 0x49c */ + u32 audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0, 0x4a0 */ + u32 audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1, 0x4a4 */ + u32 audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2, 0x4a8 */ + u32 audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3, 0x4ac */ + u32 audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4, 0x4b0 */ + u32 audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF, 0x4b4 */ + u32 plld2_base; /* _PLLD2_BASE, 0x4b8 */ + u32 plld2_misc; /* _PLLD2_MISC, 0x4bc */ + u32 utmip_pll_cfg3; /* _UTMIP_PLL_CFG3, 0x4c0 */ + u32 pllrefe_base; /* _PLLREFE_BASE, 0x4c4 */ + u32 pllrefe_misc; /* _PLLREFE_MISC, 0x4c8 */ + u32 _rsv29[7]; /* 0x4cc-4e4 */ + u32 pllc2_base; /* _PLLC2_BASE, 0x4e8 */ + u32 pllc2_misc0; /* _PLLC2_MISC_0, 0x4ec */ + u32 pllc2_misc1; /* _PLLC2_MISC_1, 0x4f0 */ + u32 pllc2_misc2; /* _PLLC2_MISC_2, 0x4f4 */ + u32 pllc2_misc3; /* _PLLC2_MISC_3, 0x4f8 */ + u32 pllc3_base; /* _PLLC3_BASE, 0x4fc */ + u32 pllc3_misc0; /* _PLLC3_MISC_0, 0x500 */ + u32 pllc3_misc1; /* _PLLC3_MISC_1, 0x504 */ + u32 pllc3_misc2; /* _PLLC3_MISC_2, 0x508 */ + u32 pllc3_misc3; /* _PLLC3_MISC_3, 0x50c */ + u32 pllx_misc1; /* _PLLX_MISC_1, 0x510 */ + u32 pllx_misc2; /* _PLLX_MISC_2, 0x514 */ + u32 pllx_misc3; /* _PLLX_MISC_3, 0x518 */ + u32 xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0, 0x51c */ + u32 xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG1, 0x520 */ + u32 plle_aux1; /* _PLLE_AUX1, 0x524 */ + u32 pllp_reshift; /* _PLLP_RESHIFT, 0x528 */ + u32 utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0, 0x52c */ + u32 pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0, 0x530 */ + u32 xusb_pll_cfg0; /* _XUSB_PLL_CFG0, 0x534 */ + u32 _rsv30; /* 0x538 */ + u32 clk_cpu_misc; /* _CLK_CPU_MISC, 0x53c */ + u32 clk_cpug_misc; /* _CLK_CPUG_MISC, 0x540 */ + u32 clk_cpulp_misc; /* _CLK_CPULP_MISC, 0x544 */ + u32 pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG, 0x548 */ + u32 pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG, 0x54c */ + u32 pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS, 0x550 */ + u32 _rsv31; /* 0x554 */ + u32 super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER, 0x558 */ + u32 spare_reg0; /* _SPARE_REG0, 0x55c */ + u32 _rsv32[4]; /* 0x560-0x56c */ + u32 plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ + u32 _rsv32_1[7]; /* 0x574-58c */ + u32 plldp_base; /* _PLLDP_BASE, 0x590 */ + u32 plldp_misc; /* _PLLDP_MISC, 0x594 */ + u32 plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ + u32 _rsrv32_2[25]; + u32 clk_src_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST 0x600 */ + u32 clk_src_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON 0x604 */ + u32 clk_src_xusb_fs; /* _CLK_SOURCE_XUSB_FS 0x608 */ + u32 clk_src_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV 0x60c */ + u32 clk_src_xusb_ss; /* _CLK_SOURCE_XUSB_SS 0x610 */ + u32 clk_src_cilab; /* _CLK_SOURCE_CILAB 0x614 */ + u32 clk_src_cilcd; /* _CLK_SOURCE_CILCD 0x618 */ + u32 clk_src_cile; /* _CLK_SOURCE_CILE 0x61c */ + u32 clk_src_dsia_lp; /* _CLK_SOURCE_DSIA_LP 0x620 */ + u32 clk_src_dsib_lp; /* _CLK_SOURCE_DSIB_LP 0x624 */ + u32 clk_src_entropy; /* _CLK_SOURCE_ENTROPY 0x628 */ + u32 clk_src_dvfs_ref; /* _CLK_SOURCE_DVFS_REF 0x62c */ + u32 clk_src_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC 0x630 */ + u32 clk_src_traceclkin; /* _CLK_SOURCE_TRACECLKIN 0x634 */ + u32 clk_src_adx0; /* _CLK_SOURCE_ADX0 0x638 */ + u32 clk_src_amx0; /* _CLK_SOURCE_AMX0 0x63c */ + u32 clk_src_emc_latency; /* _CLK_SOURCE_EMC_LATENCY 0x640 */ + u32 clk_src_soc_therm; /* _CLK_SOURCE_SOC_THERM 0x644 */ + u32 _rsv33[5]; /* 0x648-658 */ + u32 clk_src_i2c6; /* _CLK_SOURCE_I2C6, 0x65c */ +}; +check_member(clk_rst_ctlr, clk_src_i2c6, 0x65C); + +#define CLK_RST_REG(field_) \ + (&(((struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE)->field_)) + +/* L, H, U, V, W, X */ +#define DEV_CONFIG_BLOCKS 6 + +#define TEGRA_DEV_L 0 +#define TEGRA_DEV_H 1 +#define TEGRA_DEV_U 2 +#define TEGRA_DEV_V 0 +#define TEGRA_DEV_W 1 + +#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) + +/* Bits to enable/reset modules */ +#define CLK_ENB_CPU (1 << 0) +#define SWR_TRIG_SYS_RST (1 << 2) +#define SWR_CSITE_RST (1 << 9) +#define CLK_ENB_CSITE (1 << 9) + +/* CRC_SUPER_CCLK_DIVIDER_0 0x24 */ +#define SUPER_CDIV_ENB_ENABLE (1 << 31) + +/* CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48 */ +#define EN_PPSB_STOPCLK (1 << 0) + +/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 (0x4C) */ +#define CPU3_CLK_STP_SHIFT 11 +#define CPU2_CLK_STP_SHIFT 10 +#define CPU1_CLK_STP_SHIFT 9 +#define CPU0_CLK_STP_SHIFT 8 +#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT) + +/* CRC_OSC_CTRL_0 0x50 */ +#define OSC_FREQ_SHIFT 28 +#define OSC_FREQ_MASK (0xf << OSC_FREQ_SHIFT) +#define OSC_PREDIV_SHIFT 26 +#define OSC_PREDIV_MASK (0x3 << OSC_PREDIV_SHIFT) +#define OSC_XOFS_SHIFT 4 +#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT) +#define OSC_DRIVE_STRENGTH 7 +#define OSC_XOBP (1 << 1) +#define OSC_XOE (1 << 0) + +enum { + OSC_FREQ_12 = 8, /* 12.0MHz */ + OSC_FREQ_13 = 0, /* 13.0MHz */ + OSC_FREQ_16P8 = 1, /* 16.8MHz */ + OSC_FREQ_19P2 = 4, /* 19.2MHz */ + OSC_FREQ_26 = 12, /* 26.0MHz */ + OSC_FREQ_38P4 = 5, /* 38.4MHz */ + OSC_FREQ_48 = 9, /* 48.0MHz */ +}; + +/* CLK_RST_CONTROLLER_PLL*_BASE_0 */ +#define PLL_BASE_BYPASS (1U << 31) +#define PLL_BASE_ENABLE (1U << 30) +#define PLL_BASE_REF_DIS (1U << 29) +#define PLL_BASE_OVRRIDE (1U << 28) +#define PLL_BASE_LOCK (1U << 27) + +#define PLL_BASE_DIVP_SHIFT 20 +#define PLL_BASE_DIVP_MASK (7U << PLL_BASE_DIVP_SHIFT) + +#define PLL_BASE_DIVN_SHIFT 8 +#define PLL_BASE_DIVN_MASK (0x3ffU << PLL_BASE_DIVN_SHIFT) + +#define PLL_BASE_DIVM_SHIFT 0 +#define PLL_BASE_DIVM_MASK (0x1f << PLL_BASE_DIVM_SHIFT) + +/* SPECIAL CASE: PLLM, PLLC and PLLX use different-sized fields here */ +#define PLLCX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT) +#define PLLM_BASE_DIVP_MASK (0x1U << PLL_BASE_DIVP_SHIFT) +#define PLLCMX_BASE_DIVN_MASK (0xffU << PLL_BASE_DIVN_SHIFT) +#define PLLCMX_BASE_DIVM_MASK (0xffU << PLL_BASE_DIVM_SHIFT) + +/* PLLM specific registers */ +#define PLLM_MISC1_SETUP_SHIFT 0 +#define PLLM_MISC1_PD_LSHIFT_PH45_SHIFT 28 +#define PLLM_MISC1_PD_LSHIFT_PH90_SHIFT 29 +#define PLLM_MISC1_PD_LSHIFT_PH135_SHIFT 30 +#define PLLM_MISC2_KCP_SHIFT 1 +#define PLLM_MISC2_KVCO_SHIFT 0 +#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) + +/* Generic, indiscriminate divisor mask. May catch some innocent bystander bits + * on the side that we don't particularly care about. */ +#define PLL_BASE_DIV_MASK (0xffffff) + +/* CLK_RST_CONTROLLER_PLL*_OUT*_0 */ +#define PLL_OUT_RSTN (1 << 0) +#define PLL_OUT_CLKEN (1 << 1) +#define PLL_OUT_OVR (1 << 2) + +#define PLL_OUT_RATIO_SHIFT 8 +#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT) + +#define PLL_OUT1_SHIFT 0 +#define PLL_OUT2_SHIFT 16 +#define PLL_OUT3_SHIFT 0 +#define PLL_OUT4_SHIFT 16 + +/* CLK_RST_CONTROLLER_PLL*_MISC_0 */ +#define PLL_MISC_DCCON (1 << 20) + +#define PLL_MISC_CPCON_SHIFT 8 +#define PLL_MISC_CPCON_MASK (0xfU << PLL_MISC_CPCON_SHIFT) + +#define PLL_MISC_LFCON_SHIFT 4 +#define PLL_MISC_LFCON_MASK (0xfU << PLL_MISC_LFCON_SHIFT) + +/* This bit is different all over the place. Oh joy... */ +#define PLLDPD2_MISC_LOCK_ENABLE (1 << 30) +#define PLLC_MISC_LOCK_ENABLE (1 << 24) +#define PLLUD_MISC_LOCK_ENABLE (1 << 22) +#define PLLD_MISC_CLK_ENABLE (1 << 30) +#define PLLPAXS_MISC_LOCK_ENABLE (1 << 18) +#define PLLE_MISC_LOCK_ENABLE (1 << 9) + +#define PLLU_MISC_VCO_FREQ (1 << 20) + +/* PLLX_BASE_0 0xe0 */ +#define PLLX_BASE_PLLX_ENABLE (1 << 30) + +/* CLK_RST_CONTROLLER_PLLX_MISC_3 */ +#define PLLX_IDDQ_SHIFT 3 +#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT) + +#define CLK_DIVISOR_MASK (0xffff) + +#define CLK_SOURCE_SHIFT 29 +#define CLK_SOURCE_MASK (0x7 << CLK_SOURCE_SHIFT) + +#define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ (1 << 16) + +#define CLK_UART_DIV_OVERRIDE (1 << 24) + +/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ +#define SCLK_SYS_STATE_SHIFT 28U +#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT) +enum { + SCLK_SYS_STATE_STDBY, + SCLK_SYS_STATE_IDLE, + SCLK_SYS_STATE_RUN, + SCLK_SYS_STATE_IRQ = 4U, + SCLK_SYS_STATE_FIQ = 8U, +}; +#define SCLK_COP_FIQ_MASK (1 << 27) +#define SCLK_CPU_FIQ_MASK (1 << 26) +#define SCLK_COP_IRQ_MASK (1 << 25) +#define SCLK_CPU_IRQ_MASK (1 << 24) + +#define SCLK_FIQ_SHIFT 12 +#define SCLK_FIQ_MASK (7 << SCLK_FIQ_SHIFT) +#define SCLK_IRQ_SHIFT 8 +#define SCLK_IRQ_MASK (7 << SCLK_FIQ_SHIFT) +#define SCLK_RUN_SHIFT 4 +#define SCLK_RUN_MASK (7 << SCLK_FIQ_SHIFT) +#define SCLK_IDLE_SHIFT 0 +#define SCLK_IDLE_MASK (7 << SCLK_FIQ_SHIFT) +enum { + SCLK_SOURCE_CLKM, + SCLK_SOURCE_PLLC_OUT1, + SCLK_SOURCE_PLLP_OUT4, + SCLK_SOURCE_PLLP_OUT3, + SCLK_SOURCE_PLLP_OUT2, + SCLK_SOURCE_PLLC_OUT0, + SCLK_SOURCE_CLKS, + SCLK_SOURCE_PLLM_OUT1, +}; + +/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2c */ +#define SCLK_DIV_ENB (1 << 31) +#define SCLK_DIVIDEND_SHIFT 8 +#define SCLK_DIVIDEND_MASK (0xff << SCLK_DIVIDEND_SHIFT) +#define SCLK_DIVISOR_SHIFT 0 +#define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT) + +/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ +#define HCLK_DISABLE (1 << 7) +#define HCLK_DIVISOR_SHIFT 4 +#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) +#define PCLK_DISABLE (1 << 3) +#define PCLK_DIVISOR_SHIFT 0 +#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) + +/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ +#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) + +/* CRC_CLK_ENB_V_SET_0 0x440 */ +#define SET_CLK_ENB_CPUG_ENABLE (1 << 0) +#define SET_CLK_ENB_CPULP_ENABLE (1 << 1) +#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ +#define PLLU_POWERDOWN (1 << 16) +#define PLL_ENABLE_POWERDOWN (1 << 14) +#define PLL_ACTIVE_POWERDOWN (1 << 12) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */ +#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) +#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) + +// CCLK_BRST_POL +enum { + CRC_CCLK_BRST_POL_PLLX_OUT0 = 0x8, + CRC_CCLK_BRST_POL_CPU_STATE_RUN = 0x2 +}; + +// SUPER_CCLK_DIVIDER +enum { + CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31 +}; + +// CLK_CPU_CMPLX_CLR +enum { + CRC_CLK_CLR_CPU0_STP = 0x1 << 8, + CRC_CLK_CLR_CPU1_STP = 0x1 << 9, + CRC_CLK_CLR_CPU2_STP = 0x1 << 10, + CRC_CLK_CLR_CPU3_STP = 0x1 << 11 +}; + +// RST_CPUG_CMPLX_CLR +enum { + CRC_RST_CPUG_CLR_CPU0 = 0x1 << 0, + CRC_RST_CPUG_CLR_CPU1 = 0x1 << 1, + CRC_RST_CPUG_CLR_CPU2 = 0x1 << 2, + CRC_RST_CPUG_CLR_CPU3 = 0x1 << 3, + CRC_RST_CPUG_CLR_DBG0 = 0x1 << 12, + CRC_RST_CPUG_CLR_DBG1 = 0x1 << 13, + CRC_RST_CPUG_CLR_DBG2 = 0x1 << 14, + CRC_RST_CPUG_CLR_DBG3 = 0x1 << 15, + CRC_RST_CPUG_CLR_CORE0 = 0x1 << 16, + CRC_RST_CPUG_CLR_CORE1 = 0x1 << 17, + CRC_RST_CPUG_CLR_CORE2 = 0x1 << 18, + CRC_RST_CPUG_CLR_CORE3 = 0x1 << 19, + CRC_RST_CPUG_CLR_CX0 = 0x1 << 20, + CRC_RST_CPUG_CLR_CX1 = 0x1 << 21, + CRC_RST_CPUG_CLR_CX2 = 0x1 << 22, + CRC_RST_CPUG_CLR_CX3 = 0x1 << 23, + CRC_RST_CPUG_CLR_L2 = 0x1 << 24, + CRC_RST_CPUG_CLR_NONCPU = 0x1 << 29, + CRC_RST_CPUG_CLR_PDBG = 0x1 << 30, +}; + +// RST_CPULP_CMPLX_CLR +enum { + CRC_RST_CPULP_CLR_CPU0 = 0x1 << 0, + CRC_RST_CPULP_CLR_DBG0 = 0x1 << 12, + CRC_RST_CPULP_CLR_CORE0 = 0x1 << 16, + CRC_RST_CPULP_CLR_CX0 = 0x1 << 20, + CRC_RST_CPULP_CLR_L2 = 0x1 << 24, + CRC_RST_CPULP_CLR_NONCPU = 0x1 << 29, + CRC_RST_CPULP_CLR_PDBG = 0x1 << 30, +}; + +#endif /* _TEGRA132_CLK_RST_H_ */ diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h index d93e7b657f..2c7664c1ff 100644 --- a/src/soc/nvidia/tegra132/include/soc/clock.h +++ b/src/soc/nvidia/tegra132/include/soc/clock.h @@ -21,7 +21,7 @@ #include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> -#include <soc/nvidia/tegra132/clk_rst.h> +#include <soc/clk_rst.h> #include <stdint.h> #include <stdlib.h> diff --git a/src/soc/nvidia/tegra132/include/soc/clst_clk.h b/src/soc/nvidia/tegra132/include/soc/clst_clk.h new file mode 100644 index 0000000000..151ead6341 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/clst_clk.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA132_CLST_CLK_H_ +#define _TEGRA132_CLST_CLK_H_ + +/* Cluster Clock (CLUSTER_CLOCKS_PUBLIC_) regs */ +struct __attribute__ ((__packed__)) clst_clk_ctlr { + u32 pllx_base; /* _PLLX_BASE, 0x000 */ + u32 pllx_misc; /* _PLLX_MISC, 0x004 */ + u32 pllx_misc1; /* _PLLX_MISC_1, 0x008 */ + u32 pllx_misc2; /* _PLLX_MISC_2, 0x00c */ + u32 pllx_misc3; /* _PLLX_MISC_3, 0x010 */ + u32 pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG, 0x014 */ + u32 pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG, 0x018 */ + u32 pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS, 0x01c */ + u32 cclk_brst_pol; /* _CCLK_BURST_POLICY, 0x020 */ + u32 super_cclk_div; /* _SUPER_CCLK_DIVIDER, 0x024 */ + u32 _rsv1[10]; /* 0x028-04c */ + u32 shaper; /* _SHAPER, 0x050 */ + u32 shaper1; /* _SHAPER_1, 0x054 */ + u32 _rsv2[80]; /* 0x058-194 */ + u32 misc_ctrl; /* _MISC_CTRL, 0x198 */ +}; +check_member(clst_clk_ctlr, misc_ctrl, 0x198); + +/* CC_CCLK_BRST_POL */ +enum { + CC_CCLK_BRST_POL_PLLX_OUT0_LJ = 0x8, +}; + +/* CC_SUPER_CCLK_DIVIDER */ +enum { + CC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31 +}; + +/* PLLX_MISC3 */ +enum { + PLLX_IDDQ = 1 << 3, +}; + +/* MISC_CTRL */ +enum { + CLK_SWITCH_MATCH = 1 << 5, +}; + +#define CLK_SWITCH_TIMEOUT_US 1000 +#endif /* _TEGRA132_CLST_CLK_H_ */ diff --git a/src/soc/nvidia/tegra132/include/soc/dma.h b/src/soc/nvidia/tegra132/include/soc/dma.h new file mode 100644 index 0000000000..7b07cbc89b --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/dma.h @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __NVIDIA_TEGRA132_DMA_H__ +#define __NVIDIA_TEGRA132_DMA_H__ + +#include <inttypes.h> +#include <soc/addressmap.h> + +/* + * The DMA engine operates on 4 bytes at a time, so make sure any data + * passed via DMA is aligned to avoid underrun/overrun. + */ +#define TEGRA_DMA_ALIGN_BYTES 4 + +/* + * Note: Many APB DMA controller registers are laid out such that each + * bit controls or represents the status for the corresponding channel. + * So we will not bother to list each individual bit in this case. + */ +#define APB_COMMAND_GEN (1 << 31) + +#define APB_CNTRL_REG_COUNT_VALUE_MASK 0xffff +#define APB_CNTRL_REG_COUNT_VALUE_SHIFT 0 + +/* + * Note: Many APB DMA controller registers are laid out such that each + * bit controls or represents the status for the corresponding channel. + * So we will not bother to list each individual bit in this case. + */ +#define APB_COMMAND_GEN (1 << 31) + +#define APB_CNTRL_REG_COUNT_VALUE_MASK 0xffff +#define APB_CNTRL_REG_COUNT_VALUE_SHIFT 0 +struct apb_dma { + u32 command; /* 0x00 */ + u32 status; /* 0x04 */ + u32 rsvd1[2]; + u32 cntrl_reg; /* 0x10 */ + u32 irq_sta_cpu; /* 0x14 */ + u32 irq_sta_cop; /* 0x18 */ + u32 irq_mask; /* 0x1c */ + u32 irq_mask_set; /* 0x20 */ + u32 irq_mask_clr; /* 0x24 */ + u32 trig_reg; /* 0x28 */ + u32 channel_trig_reg; /* 0x2c */ + u32 dma_status; /* 0x30 */ + u32 channel_en_reg; /* 0x34 */ + u32 security_reg; /* 0x38 */ + u32 channel_swid; /* 0x3c */ + u32 rsvd[1]; + u32 chan_wt_reg0; /* 0x44 */ + u32 chan_wt_reg1; /* 0x48 */ + u32 chan_wt_reg2; /* 0x4c */ + u32 chan_wr_reg3; /* 0x50 */ + u32 channel_swid1; /* 0x54 */ +} __attribute__((packed)); +check_member(apb_dma, channel_swid1, 0x54); + +/* + * Naming in the doc included a superfluous _CHANNEL_n_ for + * each entry and was left out for the sake of conciseness. + */ +#define APB_CSR_ENB (1 << 31) +#define APB_CSR_IE_EOC (1 << 30) +#define APB_CSR_HOLD (1 << 29) +#define APB_CSR_DIR (1 << 28) +#define APB_CSR_ONCE (1 << 27) +#define APB_CSR_FLOW (1 << 21) +#define APB_CSR_REQ_SEL_MASK 0x1f +#define APB_CSR_REQ_SEL_SHIFT 16 + +enum apbdmachan_req_sel { + APBDMA_SLAVE_CNTR_REQ = 0, + APBDMA_SLAVE_APBIF_CH0 = 1, + APBDMA_SLAVE_APBIF_CH1 = 2, + APBDMA_SLAVE_APBIF_CH2 = 3, + APBDMA_SLAVE_APBIF_CH3 = 4, + APBDMA_SLAVE_HSI = 5, + APBDMA_SLAVE_APBIF_CH4 = 6, + APBDMA_SLAVE_APBIF_CH5 = 7, + APBDMA_SLAVE_UART_A = 8, + APBDMA_SLAVE_UART_B = 9, + APBDMA_SLAVE_UART_C = 10, + APBDMA_SLAVE_DTV = 11, + APBDMA_SLAVE_APBIF_CH6 = 12, + APBDMA_SLAVE_APBIF_CH7 = 13, + APBDMA_SLAVE_APBIF_CH8 = 14, + APBDMA_SLAVE_SL2B1 = 15, + APBDMA_SLAVE_SL2B2 = 16, + APBDMA_SLAVE_SL2B3 = 17, + APBDMA_SLAVE_SL2B4 = 18, + APBDMA_SLAVE_UART_D = 19, + APBDMA_SLAVE_UART_E = 20, + APBDMA_SLAVE_I2C = 21, + APBDMA_SLAVE_I2C2 = 22, + APBDMA_SLAVE_I2C3 = 23, + APBDMA_SLAVE_DVC_I2C = 24, + APBDMA_SLAVE_OWR = 25, + APBDMA_SLAVE_I2C4 = 26, + APBDMA_SLAVE_SL2B5 = 27, + APBDMA_SLAVE_SL2B6 = 28, + APBDMA_SLAVE_APBIF_CH9 = 29, + APBDMA_SLAVE_I2C6 = 30, + APBDMA_SLAVE_NA31 = 31, +}; + +#define APB_STA_BSY (1 << 31) +#define APB_STA_ISE_EOC (1 << 30) +#define APB_STA_HALT (1 << 29) +#define APB_STA_PING_PONG_STA (1 << 28) +#define APB_STA_DMA_ACTIVITY (1 << 27) +#define APB_STA_CHANNEL_PAUSE (1 << 26) + +#define APB_CSRE_CHANNEL_PAUSE (1 << 31) +#define APB_CSRE_TRIG_SEL_MASK 0x3f +#define APB_CSRE_TRIG_SEL_SHIFT 14 + +#define AHB_PTR_MASK (0x3fffffff) +#define AHB_PTR_SHIFT 2 + +#define AHB_SEQ_INTR_ENB (1 << 31) +#define AHB_BUS_WIDTH_MASK 0x7 +#define AHB_BUS_WIDTH_SHIFT 28 +#define AHB_DATA_SWAP (1 << 27) +#define AHB_BURST_MASK 0x7 +#define AHB_BURST_SHIFT 24 +#define AHB_SEQ_DBL_BUF (1 << 19) +#define AHB_SEQ_WRAP_MASK 0x7 +#define AHB_SEQ_WRAP_SHIFT 16 + +#define APB_PTR_MASK 0x3fffffff +#define APB_PTR_SHIFT 2 + +#define APB_BUS_WIDTH_MASK 0x7 +#define APB_BUS_WIDTH_SHIFT 28 +#define APB_DATA_SWAP (1 << 27) +#define APB_ADDR_WRAP_MASK 0x7 +#define APB_ADDR_WRAP_SHIFT 16 + +#define APB_WORD_TRANSFER_MASK 0x0fffffff +#define APB_WORD_TRANSFER_SHIFT 2 + +struct apb_dma_channel_regs { + u32 csr; /* 0x00 */ + u32 sta; /* 0x04 */ + u32 dma_byte_sta; /* 0x08 */ + u32 csre; /* 0x0c */ + u32 ahb_ptr; /* 0x10 */ + u32 ahb_seq; /* 0x14 */ + u32 apb_ptr; /* 0x18 */ + u32 apb_seq; /* 0x1c */ + u32 wcount; /* 0x20 */ + u32 word_transfer; /* 0x24 */ +} __attribute__((packed)); +check_member(apb_dma_channel_regs, word_transfer, 0x24); + +struct apb_dma_channel { + const int num; + struct apb_dma_channel_regs *regs; + + /* + * Basic high-level semaphore that can be used to "claim" + * a DMA channel e.g. by SPI, I2C, or other peripheral driver. + */ + int in_use; +}; + +struct apb_dma_channel * const dma_claim(void); +void dma_release(struct apb_dma_channel * const channel); +int dma_start(struct apb_dma_channel * const channel); +int dma_stop(struct apb_dma_channel * const channel); +int dma_busy(struct apb_dma_channel * const channel); + +#endif /* __NVIDIA_TEGRA132_DMA_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/emc.h b/src/soc/nvidia/tegra132/include/soc/emc.h new file mode 100644 index 0000000000..2aa814fc41 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/emc.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA132_EMC_H__ +#define __SOC_NVIDIA_TEGRA132_EMC_H__ + +#include <stddef.h> +#include <stdint.h> + +enum { + EMC_PIN_RESET_MASK = 1 << 8, + EMC_PIN_RESET_ACTIVE = 0 << 8, + EMC_PIN_RESET_INACTIVE = 1 << 8, + EMC_PIN_DQM_MASK = 1 << 4, + EMC_PIN_DQM_NORMAL = 0 << 4, + EMC_PIN_DQM_INACTIVE = 1 << 4, + EMC_PIN_CKE_MASK = 1 << 0, + EMC_PIN_CKE_POWERDOWN = 0 << 0, + EMC_PIN_CKE_NORMAL = 1 << 0, + + EMC_REF_CMD_MASK = 1 << 0, + EMC_REF_CMD_REFRESH = 1 << 0, + EMC_REF_NORMAL_MASK = 1 << 1, + EMC_REF_NORMAL_INIT = 0 << 1, + EMC_REF_NORMAL_ENABLED = 1 << 1, + EMC_REF_NUM_SHIFT = 8, + EMC_REF_NUM_MASK = 0xFF << EMC_REF_NUM_SHIFT, + EMC_REF_DEV_SELECTN_SHIFT = 30, + EMC_REF_DEV_SELECTN_MASK = 3 << EMC_REF_DEV_SELECTN_SHIFT, + + EMC_REFCTRL_REF_VALID_MASK = 1 << 31, + EMC_REFCTRL_REF_VALID_DISABLED = 0 << 31, + EMC_REFCTRL_REF_VALID_ENABLED = 1 << 31, + + EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK = 1 << 1, + EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK = 1 << 2, + EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK = 1 << 3, + + EMC_NOP_NOP_CMD_SHIFT = 0, + EMC_NOP_NOP_CMD_MASK = 1 << EMC_NOP_NOP_CMD_SHIFT, + EMC_NOP_NOP_DEV_SELECTN_SHIFT = 30, + EMC_NOP_NOP_DEV_SELECTN_MASK = 3 << EMC_NOP_NOP_DEV_SELECTN_SHIFT, + + EMC_TIMING_CONTROL_TIMING_UPDATE = 1, +}; + +struct tegra_emc_regs { + uint32_t intstatus; /* 0x0 */ + uint32_t intmask; /* 0x4 */ + uint32_t dbg; /* 0x8 */ + uint32_t cfg; /* 0xc */ + uint32_t adr_cfg; /* 0x10 */ + uint32_t rsvd_0x14[3]; /* 0x14 */ + + uint32_t refctrl; /* 0x20 */ + uint32_t pin; /* 0x24 */ + uint32_t timing_control; /* 0x28 */ + uint32_t rc; /* 0x2c */ + uint32_t rfc; /* 0x30 */ + uint32_t ras; /* 0x34 */ + uint32_t rp; /* 0x38 */ + uint32_t r2w; /* 0x3c */ + uint32_t w2r; /* 0x40 */ + uint32_t r2p; /* 0x44 */ + uint32_t w2p; /* 0x48 */ + uint32_t rd_rcd; /* 0x4c */ + uint32_t wr_rcd; /* 0x50 */ + uint32_t rrd; /* 0x54 */ + uint32_t rext; /* 0x58 */ + uint32_t wdv; /* 0x5c */ + uint32_t quse; /* 0x60 */ + uint32_t qrst; /* 0x64 */ + uint32_t qsafe; /* 0x68 */ + uint32_t rdv; /* 0x6c */ + uint32_t refresh; /* 0x70 */ + uint32_t burst_refresh_num; /* 0x74 */ + uint32_t pdex2wr; /* 0x78 */ + uint32_t pdex2rd; /* 0x7c */ + uint32_t pchg2pden; /* 0x80 */ + uint32_t act2pden; /* 0x84 */ + uint32_t ar2pden; /* 0x88 */ + uint32_t rw2pden; /* 0x8c */ + uint32_t txsr; /* 0x90 */ + uint32_t tcke; /* 0x94 */ + uint32_t tfaw; /* 0x98 */ + uint32_t trpab; /* 0x9c */ + uint32_t tclkstable; /* 0xa0 */ + uint32_t tclkstop; /* 0xa4 */ + uint32_t trefbw; /* 0xa8 */ + uint32_t rsvd_0xac[1]; /* 0xac */ + uint32_t odt_write; /* 0xb0 */ + uint32_t odt_read; /* 0xb4 */ + uint32_t wext; /* 0xb8 */ + uint32_t ctt; /* 0xbc */ + uint32_t rfc_slr; /* 0xc0 */ + uint32_t mrs_wait_cnt2; /* 0xc4 */ + uint32_t mrs_wait_cnt; /* 0xc8 */ + uint32_t mrs; /* 0xcc */ + uint32_t emrs; /* 0xd0 */ + uint32_t ref; /* 0xd4 */ + uint32_t pre; /* 0xd8 */ + uint32_t nop; /* 0xdc */ + uint32_t self_ref; /* 0xe0 */ + uint32_t dpd; /* 0xe4 */ + uint32_t mrw; /* 0xe8 */ + uint32_t mrr; /* 0xec */ + uint32_t cmdq; /* 0xf0 */ + uint32_t mc2emcq; /* 0xf4 */ + uint32_t xm2dqspadctrl3; /* 0xf8 */ + uint32_t rsvd_0xfc[1]; /* 0xfc */ + uint32_t fbio_spare; /* 0x100 */ + uint32_t fbio_cfg5; /* 0x104 */ + uint32_t fbio_wrptr_eq_2; /* 0x108 */ + uint32_t rsvd_0x10c[2]; /* 0x10c */ + + uint32_t fbio_cfg6; /* 0x114 */ + uint32_t rsvd_0x118[2]; /* 0x118 */ + + uint32_t cfg_rsv; /* 0x120 */ + uint32_t acpd_control; /* 0x132 */ + uint32_t rsvd_0x128[1]; /* 0x128 */ + uint32_t emrs2; /* 0x12c */ + uint32_t emrs3; /* 0x130 */ + uint32_t mrw2; /* 0x134 */ + uint32_t mrw3; /* 0x138 */ + uint32_t mrw4; /* 0x13c */ + uint32_t clken_override; /* 0x140 */ + uint32_t r2r; /* 0x144 */ + uint32_t w2w; /* 0x148 */ + uint32_t einput; /* 0x14c */ + uint32_t einput_duration; /* 0x150 */ + uint32_t puterm_extra; /* 0x154 */ + uint32_t tckesr; /* 0x158 */ + uint32_t tpd; /* 0x15c */ + uint32_t rsvd_0x160[81]; /* 0x160 */ + + uint32_t auto_cal_config; /* 0x2a4 */ + uint32_t auto_cal_interval; /* 0x2a8 */ + uint32_t auto_cal_status; /* 0x2ac */ + uint32_t req_ctrl; /* 0x2b0 */ + uint32_t status; /* 0x2b4 */ + uint32_t cfg_2; /* 0x2b8 */ + uint32_t cfg_dig_dll; /* 0x2bc */ + uint32_t cfg_dig_dll_period; /* 0x2c0 */ + uint32_t rsvd_0x2c4[1]; /* 0x2c4 */ + uint32_t dig_dll_status; /* 0x2c8 */ + uint32_t rdv_mask; /* 0x2cc */ + uint32_t wdv_mask; /* 0x2d0 */ + uint32_t rsvd_0x2d4[1]; /* 0x2d4 */ + uint32_t ctt_duration; /* 0x2d8 */ + uint32_t ctt_term_ctrl; /* 0x2dc */ + uint32_t zcal_interval; /* 0x2e0 */ + uint32_t zcal_wait_cnt; /* 0x2e4 */ + uint32_t zcal_mrw_cmd; /* 0x2e8 */ + uint32_t zq_cal; /* 0x2ec */ + uint32_t xm2cmdpadctrl; /* 0x2f0 */ + uint32_t xm2cmdpadctrl2; /* 0x2f4 */ + uint32_t xm2dqspadctrl; /* 0x2f8 */ + uint32_t xm2dqspadctrl2; /* 0x2fc */ + uint32_t xm2dqpadctrl; /* 0x300 */ + uint32_t xm2dqpadctrl2; /* 0x304 */ + uint32_t xm2clkpadctrl; /* 0x308 */ + uint32_t xm2comppadctrl; /* 0x30c */ + uint32_t xm2vttgenpadctrl; /* 0x310 */ + uint32_t xm2vttgenpadctrl2; /* 0x314 */ + uint32_t xm2vttgenpadctrl3; /* 0x318 */ + uint32_t emcpaden; /* 0x31c */ + uint32_t xm2dqspadctrl4; /* 0x320 */ + uint32_t scratch0; /* 0x324 */ + uint32_t dll_xform_dqs0; /* 0x328 */ + uint32_t dll_xform_dqs1; /* 0x32c */ + uint32_t dll_xform_dqs2; /* 0x330 */ + uint32_t dll_xform_dqs3; /* 0x334 */ + uint32_t dll_xform_dqs4; /* 0x338 */ + uint32_t dll_xform_dqs5; /* 0x33c */ + uint32_t dll_xform_dqs6; /* 0x340 */ + uint32_t dll_xform_dqs7; /* 0x344 */ + uint32_t dll_xform_quse0; /* 0x348 */ + uint32_t dll_xform_quse1; /* 0x34c */ + uint32_t dll_xform_quse2; /* 0x350 */ + uint32_t dll_xform_quse3; /* 0x354 */ + uint32_t dll_xform_quse4; /* 0x358 */ + uint32_t dll_xform_quse5; /* 0x35c */ + uint32_t dll_xform_quse6; /* 0x360 */ + uint32_t dll_xform_quse7; /* 0x364 */ + uint32_t dll_xform_dq0; /* 0x368 */ + uint32_t dll_xform_dq1; /* 0x36c */ + uint32_t dll_xform_dq2; /* 0x370 */ + uint32_t dll_xform_dq3; /* 0x374 */ + uint32_t dli_rx_trim0; /* 0x378 */ + uint32_t dli_rx_trim1; /* 0x37c */ + uint32_t dli_rx_trim2; /* 0x380 */ + uint32_t dli_rx_trim3; /* 0x384 */ + uint32_t dli_rx_trim4; /* 0x388 */ + uint32_t dli_rx_trim5; /* 0x38c */ + uint32_t dli_rx_trim6; /* 0x390 */ + uint32_t dli_rx_trim7; /* 0x394 */ + uint32_t dli_tx_trim0; /* 0x398 */ + uint32_t dli_tx_trim1; /* 0x39c */ + uint32_t dli_tx_trim2; /* 0x3a0 */ + uint32_t dli_tx_trim3; /* 0x3a4 */ + uint32_t dli_trim_txdqs0; /* 0x3a8 */ + uint32_t dli_trim_txdqs1; /* 0x3ac */ + uint32_t dli_trim_txdqs2; /* 0x3b0 */ + uint32_t dli_trim_txdqs3; /* 0x3b4 */ + uint32_t dli_trim_txdqs4; /* 0x3b8 */ + uint32_t dli_trim_txdqs5; /* 0x3bc */ + uint32_t dli_trim_txdqs6; /* 0x3c0 */ + uint32_t dli_trim_txdqs7; /* 0x3c4 */ + uint32_t rsvd_0x3c8[1]; /* 0x3c8 */ + uint32_t stall_then_exe_after_clkchange; /* 0x3cc */ + uint32_t rsvd_0x3d0[1]; /* 0x3d0 */ + uint32_t auto_cal_clk_status; /* 0x3d4 */ + uint32_t sel_dpd_ctrl; /* 0x3d8 */ + uint32_t pre_refresh_req_cnt; /* 0x3dc */ + uint32_t dyn_self_ref_control; /* 0x3e0 */ + uint32_t txsrdll; /* 0x3e4 */ + uint32_t ccfifo_addr; /* 0x3e8 */ + uint32_t ccfifo_data; /* 0x3ec */ + uint32_t ccfifo_status; /* 0x3f0 */ + uint32_t cdb_cntl_1; /* 0x3f4 */ + uint32_t cdb_cntl_2; /* 0x3f8 */ + uint32_t xm2clkpadctrl2; /* 0x3fc */ + uint32_t swizzle_rank0_byte_cfg; /* 0x400 */ + uint32_t swizzle_rank0_byte0; /* 0x404 */ + uint32_t swizzle_rank0_byte1; /* 0x408 */ + uint32_t swizzle_rank0_byte2; /* 0x40c */ + uint32_t swizzle_rank0_byte3; /* 0x410 */ + uint32_t swizzle_rank1_byte_cfg; /* 0x414 */ + uint32_t swizzle_rank1_byte0; /* 0x418 */ + uint32_t swizzle_rank1_byte1; /* 0x41c */ + uint32_t swizzle_rank1_byte2; /* 0x420 */ + uint32_t swizzle_rank1_byte3; /* 0x424 */ + uint32_t ca_training_start; /* 0x428 */ + uint32_t ca_training_busy; /* 0x42c */ + uint32_t ca_training_cfg; /* 0x430 */ + uint32_t ca_training_timing_cntl1; /* 0x434 */ + uint32_t ca_training_timing_cntl2; /* 0x438 */ + uint32_t ca_training_ca_lead_in; /* 0x43c */ + uint32_t ca_training_ca; /* 0x440 */ + uint32_t ca_training_ca_lead_out; /* 0x444 */ + uint32_t ca_training_result1; /* 0x448 */ + uint32_t ca_training_result2; /* 0x44c */ + uint32_t ca_training_result3; /* 0x450 */ + uint32_t ca_training_result4; /* 0x454 */ + uint32_t auto_cal_config2; /* 0x458 */ + uint32_t auto_cal_config3; /* 0x45c */ + uint32_t auto_cal_status2; /* 0x460 */ + uint32_t xm2cmdpadctrl3; /* 0x464 */ + uint32_t ibdly; /* 0x468 */ + uint32_t dll_xform_addr0; /* 0x46c */ + uint32_t dll_xform_addr1; /* 0x470 */ + uint32_t dll_xform_addr2; /* 0x474 */ + uint32_t dli_addr_trim; /* 0x478 */ + uint32_t dsr_vttgen_drv; /* 0x47c */ + uint32_t txdsrvttgen; /* 0x480 */ + uint32_t xm2cmdpadctrl4; /* 0x484 */ + uint32_t xm2cmdpadctrl5; /* 0x488 */ + uint32_t rsvd_0x48c[5]; /* 0x48c */ + + uint32_t dll_xform_dqs8; /* 0x4a0 */ + uint32_t dll_xform_dqs9; /* 0x4a4 */ + uint32_t dll_xform_dqs10; /* 0x4a8 */ + uint32_t dll_xform_dqs11; /* 0x4ac */ + uint32_t dll_xform_dqs12; /* 0x4b0 */ + uint32_t dll_xform_dqs13; /* 0x4b4 */ + uint32_t dll_xform_dqs14; /* 0x4b8 */ + uint32_t dll_xform_dqs15; /* 0x4bc */ + uint32_t dll_xform_quse8; /* 0x4c0 */ + uint32_t dll_xform_quse9; /* 0x4c4 */ + uint32_t dll_xform_quse10; /* 0x4c8 */ + uint32_t dll_xform_quse11; /* 0x4cc */ + uint32_t dll_xform_quse12; /* 0x4d0 */ + uint32_t dll_xform_quse13; /* 0x4d4 */ + uint32_t dll_xform_quse14; /* 0x4d8 */ + uint32_t dll_xform_quse15; /* 0x4dc */ + uint32_t dll_xform_dq4; /* 0x4e0 */ + uint32_t dll_xform_dq5; /* 0x4e4 */ + uint32_t dll_xform_dq6; /* 0x4e8 */ + uint32_t dll_xform_dq7; /* 0x4ec */ + uint32_t rsvd_0x4f0[12]; /* 0x4f0 */ + + uint32_t dli_trim_txdqs8; /* 0x520 */ + uint32_t dli_trim_txdqs9; /* 0x524 */ + uint32_t dli_trim_txdqs10; /* 0x528 */ + uint32_t dli_trim_txdqs11; /* 0x52c */ + uint32_t dli_trim_txdqs12; /* 0x530 */ + uint32_t dli_trim_txdqs13; /* 0x534 */ + uint32_t dli_trim_txdqs14; /* 0x538 */ + uint32_t dli_trim_txdqs15; /* 0x53c */ + uint32_t cdb_cntl_3; /* 0x540 */ + uint32_t xm2dqspadctrl5; /* 0x544 */ + uint32_t xm2dqspadctrl6; /* 0x548 */ + uint32_t xm2dqpadctrl3; /* 0x54c */ + uint32_t dll_xform_addr3; /* 0x550 */ + uint32_t dll_xform_addr4; /* 0x554 */ + uint32_t dll_xform_addr5; /* 0x558 */ + uint32_t rsvd_0x55c[1]; /* 0x55c */ + uint32_t cfg_pipe; /* 0x560 */ + uint32_t qpop; /* 0x564 */ + uint32_t quse_width; /* 0x568 */ + uint32_t puterm_width; /* 0x56c */ + uint32_t bgbias_ctl0; /* 0x570 */ + uint32_t puterm_adj; /* 0x574 */ +} __attribute__((packed)); + +check_member(tegra_emc_regs, puterm_adj, 0x574); + +#endif /* __SOC_NVIDIA_TEGRA132_EMC_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/flow.h b/src/soc/nvidia/tegra132/include/soc/flow.h new file mode 100644 index 0000000000..01dbc14208 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/flow.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA132_FLOW_H_ +#define _TEGRA132_FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; /* offset 0x00 */ + u32 halt_cop_events; /* offset 0x04 */ + u32 cpu_csr; /* offset 0x08 */ + u32 cop_csr; /* offset 0x0c */ + u32 xrq_events; /* offset 0x10 */ + u32 halt_cpu1_events; /* offset 0x14 */ + u32 cpu1_csr; /* offset 0x18 */ + u32 halt_cpu2_events; /* offset 0x1c */ + u32 cpu2_csr; /* offset 0x20 */ + u32 halt_cpu3_events; /* offset 0x24 */ + u32 cpu3_csr; /* offset 0x28 */ + u32 cluster_control; /* offset 0x2c */ + u32 halt_cop1_events; /* offset 0x30 */ + u32 halt_cop1_csr; /* offset 0x34 */ + u32 cpu_pwr_csr; /* offset 0x38 */ + u32 mpid; /* offset 0x3c */ + u32 ram_repair; /* offset 0x40 */ +}; +check_member(flow_ctlr, ram_repair, 0x40); + +enum { + FLOW_MODE_SHIFT = 29, + FLOW_MODE_MASK = 0x7 << FLOW_MODE_SHIFT, + + FLOW_MODE_NONE = 0 << FLOW_MODE_SHIFT, + FLOW_MODE_RUN_AND_INT = 1 << FLOW_MODE_SHIFT, + FLOW_MODE_WAITEVENT = 2 << FLOW_MODE_SHIFT, + FLOW_MODE_WAITEVENT_AND_INT = 3 << FLOW_MODE_SHIFT, + FLOW_MODE_STOP_UNTIL_IRQ = 4 << FLOW_MODE_SHIFT, + FLOW_MODE_STOP_UNTIL_IRQ_AND_INT = 5 << FLOW_MODE_SHIFT, + FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ = 6 << FLOW_MODE_SHIFT, +}; + +/* HALT_COP_EVENTS_0, 0x04 */ +enum { + FLOW_EVENT_GIC_FIQ = 1 << 8, + FLOW_EVENT_GIC_IRQ = 1 << 9, + FLOW_EVENT_LIC_FIQ = 1 << 10, + FLOW_EVENT_LIC_IRQ = 1 << 11, + FLOW_EVENT_IBF = 1 << 12, + FLOW_EVENT_IBE = 1 << 13, + FLOW_EVENT_OBF = 1 << 14, + FLOW_EVENT_OBE = 1 << 15, + FLOW_EVENT_XRQ_A = 1 << 16, + FLOW_EVENT_XRQ_B = 1 << 17, + FLOW_EVENT_XRQ_C = 1 << 18, + FLOW_EVENT_XRQ_D = 1 << 19, + FLOW_EVENT_SMP30 = 1 << 20, + FLOW_EVENT_SMP31 = 1 << 21, + FLOW_EVENT_X_RDY = 1 << 22, + FLOW_EVENT_SEC = 1 << 23, + FLOW_EVENT_MSEC = 1 << 24, + FLOW_EVENT_USEC = 1 << 25, + FLOW_EVENT_X32K = 1 << 26, + FLOW_EVENT_SCLK = 1 << 27, + FLOW_EVENT_JTAG = 1 << 28 +}; + +#endif /* _TEGRA132_FLOW_H_ */ diff --git a/src/soc/nvidia/tegra132/include/soc/funitcfg.h b/src/soc/nvidia/tegra132/include/soc/funitcfg.h index cf49d0ab8c..2c680fe374 100644 --- a/src/soc/nvidia/tegra132/include/soc/funitcfg.h +++ b/src/soc/nvidia/tegra132/include/soc/funitcfg.h @@ -20,10 +20,10 @@ #ifndef __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H #define __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H -#include <stdint.h> -#include <soc/nvidia/tegra132/pinmux.h> -#include <soc/padconfig.h> #include <soc/clock.h> +#include <soc/padconfig.h> +#include <soc/pinmux.h> +#include <stdint.h> #define FUNIT_INDEX(_name) FUNIT_##_name diff --git a/src/soc/nvidia/tegra132/include/soc/gpio.h b/src/soc/nvidia/tegra132/include/soc/gpio.h new file mode 100644 index 0000000000..b28a87f687 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/gpio.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_GPIO_H__ +#define __SOC_NVIDIA_TEGRA132_GPIO_H__ + +#include <soc/pinmux.h> + +#endif /* __SOC_NVIDIA_TEGRA132_GPIO_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/maincpu.h b/src/soc/nvidia/tegra132/include/soc/maincpu.h new file mode 100644 index 0000000000..1f795dfc66 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/maincpu.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_MAINCPU_H__ +#define __SOC_NVIDIA_TEGRA132_MAINCPU_H__ + +#include <stdint.h> + +extern u32 maincpu_stack_pointer; +extern u32 maincpu_entry_point; +void maincpu_setup(void); + +#endif /* __SOC_NVIDIA_TEGRA132_MAINCPU_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/mc.h b/src/soc/nvidia/tegra132/include/soc/mc.h new file mode 100644 index 0000000000..3ce790022b --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/mc.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA132_MC_H__ +#define __SOC_NVIDIA_TEGRA132_MC_H__ + +#include <stddef.h> +#include <stdint.h> + +// Memory Controller registers we need/care about + +struct tegra_mc_regs { + uint32_t rsvd_0x0[4]; /* 0x00 */ + uint32_t smmu_config; /* 0x10 */ + uint32_t smmu_tlb_config; /* 0x14 */ + uint32_t smmu_ptc_config; /* 0x18 */ + uint32_t smmu_ptb_asid; /* 0x1c */ + uint32_t smmu_ptb_data; /* 0x20 */ + uint32_t rsvd_0x24[3]; /* 0x24 */ + uint32_t smmu_tlb_flush; /* 0x30 */ + uint32_t smmu_ptc_flush; /* 0x34 */ + uint32_t rsvd_0x38[6]; /* 0x38 */ + uint32_t emem_cfg; /* 0x50 */ + uint32_t emem_adr_cfg; /* 0x54 */ + uint32_t emem_adr_cfg_dev0; /* 0x58 */ + uint32_t emem_adr_cfg_dev1; /* 0x5c */ + uint32_t rsvd_0x60[1]; /* 0x60 */ + uint32_t emem_adr_cfg_bank_mask_0; /* 0x64 */ + uint32_t emem_adr_cfg_bank_mask_1; /* 0x68 */ + uint32_t emem_adr_cfg_bank_mask_2; /* 0x6c */ + uint32_t security_cfg0; /* 0x70 */ + uint32_t security_cfg1; /* 0x74 */ + uint32_t rsvd_0x78[6]; /* 0x78 */ + uint32_t emem_arb_cfg; /* 0x90 */ + uint32_t emem_arb_outstanding_req; /* 0x94 */ + uint32_t emem_arb_timing_rcd; /* 0x98 */ + uint32_t emem_arb_timing_rp; /* 0x9c */ + uint32_t emem_arb_timing_rc; /* 0xa0 */ + uint32_t emem_arb_timing_ras; /* 0xa4 */ + uint32_t emem_arb_timing_faw; /* 0xa8 */ + uint32_t emem_arb_timing_rrd; /* 0xac */ + uint32_t emem_arb_timing_rap2pre; /* 0xb0 */ + uint32_t emem_arb_timing_wap2pre; /* 0xb4 */ + uint32_t emem_arb_timing_r2r; /* 0xb8 */ + uint32_t emem_arb_timing_w2w; /* 0xbc */ + uint32_t emem_arb_timing_r2w; /* 0xc0 */ + uint32_t emem_arb_timing_w2r; /* 0xc4 */ + uint32_t rsvd_0xc8[2]; /* 0xc8 */ + uint32_t emem_arb_da_turns; /* 0xd0 */ + uint32_t emem_arb_da_covers; /* 0xd4 */ + uint32_t emem_arb_misc0; /* 0xd8 */ + uint32_t emem_arb_misc1; /* 0xdc */ + uint32_t emem_arb_ring1_throttle; /* 0xe0 */ + uint32_t emem_arb_ring3_throttle; /* 0xe4 */ + uint32_t emem_arb_override; /* 0xe8 */ + uint32_t emem_arb_rsv; /* 0xec */ + uint32_t rsvd_0xf0[1]; /* 0xf0 */ + uint32_t clken_override; /* 0xf4 */ + uint32_t timing_control_dbg; /* 0xf8 */ + uint32_t timing_control; /* 0xfc */ + uint32_t stat_control; /* 0x100 */ + uint32_t rsvd_0x104[65]; /* 0x104 */ + uint32_t emem_arb_isochronous_0; /* 0x208 */ + uint32_t emem_arb_isochronous_1; /* 0x20c */ + uint32_t emem_arb_isochronous_2; /* 0x210 */ + uint32_t rsvd_0x214[38]; /* 0x214 */ + uint32_t dis_extra_snap_levels; /* 0x2ac */ + uint32_t rsvd_0x2b0[90]; /* 0x2b0 */ + uint32_t video_protect_vpr_override; /* 0x418 */ + uint32_t rsvd_0x41c[93]; /* 0x41c */ + uint32_t video_protect_vpr_override1; /* 0x590 */ + uint32_t rsvd_0x594[29]; /* 0x594 */ + uint32_t display_snap_ring; /* 0x608 */ + uint32_t rsvd_0x60c[15]; /* 0x60c */ + uint32_t video_protect_bom; /* 0x648 */ + uint32_t video_protect_size_mb; /* 0x64c */ + uint32_t video_protect_reg_ctrl; /* 0x650 */ + uint32_t rsvd_0x654[4]; /* 0x654 */ + uint32_t emem_cfg_access_ctrl; /* 0x664 */ + uint32_t rsvd_0x668[2]; /* 0x668 */ + uint32_t sec_carveout_bom; /* 0x670 */ + uint32_t sec_carveout_size_mb; /* 0x674 */ + uint32_t sec_carveout_reg_ctrl; /* 0x678 */ + uint32_t rsvd_0x67c[187]; /* 0x67c */ + uint32_t emem_arb_override_1; /* 0x968 */ + uint32_t rsvd_0x96c[3]; /* 0x96c */ + uint32_t video_protect_bom_adr_hi; /* 0x978 */ + uint32_t rsvd_0x97c[2]; /* 0x97c */ + uint32_t video_protect_gpu_override_0; /* 0x984 */ + uint32_t video_protect_gpu_override_1; /* 0x988 */ + uint32_t rsvd_0x98c[5]; /* 0x98c */ + uint32_t mts_carveout_bom; /* 0x9a0 */ + uint32_t mts_carveout_size_mb; /* 0x9a4 */ + uint32_t mts_carveout_adr_hi; /* 0x9a8 */ + uint32_t mts_carveout_reg_ctrl; /* 0x9ac */ + uint32_t rsvd_0x9b0[4]; /* 0x9b0 */ + uint32_t emem_bank_swizzle_cfg0; /* 0x9c0 */ + uint32_t emem_bank_swizzle_cfg1; /* 0x9c4 */ + uint32_t emem_bank_swizzle_cfg2; /* 0x9c8 */ + uint32_t emem_bank_swizzle_cfg3; /* 0x9cc */ + uint32_t rsvd_0x9d0[1]; /* 0x9d0 */ + uint32_t sec_carveout_adr_hi; /* 0x9d4 */ +}; + +enum { + MC_SMMU_CONFIG_ENABLE = 1, + + MC_EMEM_CFG_SIZE_MB_SHIFT = 0, + MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff, + + MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27, + MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27, + + MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED = 1, + + MC_TIMING_CONTROL_TIMING_UPDATE = 1, +}; + +check_member(tegra_mc_regs, sec_carveout_adr_hi, 0x9d4); + +#endif /* __SOC_NVIDIA_TEGRA132_MC_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout.ld b/src/soc/nvidia/tegra132/include/soc/memlayout.ld new file mode 100644 index 0000000000..63cf4f031c --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/memlayout.ld @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, + * so the bootblock loading address must be placed after that. After the + * handoff that area may be reclaimed for other uses, e.g. CBFS cache. + * TODO: Did this change on Tegra132? What's the new valid range? + */ + +SECTIONS +{ + SRAM_START(0x40000000) + /* 16K hole */ + PRERAM_CBMEM_CONSOLE(0x40004000, 8K) + CBFS_CACHE(0x40006000, 88K) + STACK(0x4001C000, 16K) + BOOTBLOCK(0x40020000, 20K) + ROMSTAGE(0x40025000, 108K) + SRAM_END(0x40040000) + + DRAM_START(0x80000000) + RAMSTAGE(0x80200000, 192K) +} diff --git a/src/soc/nvidia/tegra132/include/soc/mmu_operations.h b/src/soc/nvidia/tegra132/include/soc/mmu_operations.h new file mode 100644 index 0000000000..8c82b26477 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/mmu_operations.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__ +#define __SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__ + +void tegra132_mmu_init(void); + +/* Default ttb size of 1MiB */ +#define TTB_SIZE 0x1 + +#endif //__SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__ diff --git a/src/soc/nvidia/tegra132/include/soc/padconfig.h b/src/soc/nvidia/tegra132/include/soc/padconfig.h index a4339891f2..569fe4624c 100644 --- a/src/soc/nvidia/tegra132/include/soc/padconfig.h +++ b/src/soc/nvidia/tegra132/include/soc/padconfig.h @@ -21,7 +21,7 @@ #define __SOC_NVIDIA_TEGRA132_PAD_CFG_H #include <stdint.h> -#include <soc/nvidia/tegra132/pinmux.h> +#include <soc/pinmux.h> struct pad_config { uint8_t pinmux_flags; /* PU/PU, OD, INPUT, SFIO, etc */ diff --git a/src/soc/nvidia/tegra132/include/soc/pinmux.h b/src/soc/nvidia/tegra132/include/soc/pinmux.h new file mode 100644 index 0000000000..f3bab1da01 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/pinmux.h @@ -0,0 +1,292 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_PINMUX_H__ +#define __SOC_NVIDIA_TEGRA132_PINMUX_H__ + +#include <stdint.h> +#include <soc/nvidia/tegra/gpio.h> +#include <soc/nvidia/tegra/pinmux.h> + +/* GPIO index constants. */ + +#define GPIO_PORT_CONSTANTS(port) \ + GPIO_##port##0_INDEX, GPIO_##port##1_INDEX, GPIO_##port##2_INDEX, \ + GPIO_##port##3_INDEX, GPIO_##port##4_INDEX, GPIO_##port##5_INDEX, \ + GPIO_##port##6_INDEX, GPIO_##port##7_INDEX + +enum { + GPIO_PORT_CONSTANTS(A), + GPIO_PORT_CONSTANTS(B), + GPIO_PORT_CONSTANTS(C), + GPIO_PORT_CONSTANTS(D), + GPIO_PORT_CONSTANTS(E), + GPIO_PORT_CONSTANTS(F), + GPIO_PORT_CONSTANTS(G), + GPIO_PORT_CONSTANTS(H), + GPIO_PORT_CONSTANTS(I), + GPIO_PORT_CONSTANTS(J), + GPIO_PORT_CONSTANTS(K), + GPIO_PORT_CONSTANTS(L), + GPIO_PORT_CONSTANTS(M), + GPIO_PORT_CONSTANTS(N), + GPIO_PORT_CONSTANTS(O), + GPIO_PORT_CONSTANTS(P), + GPIO_PORT_CONSTANTS(Q), + GPIO_PORT_CONSTANTS(R), + GPIO_PORT_CONSTANTS(S), + GPIO_PORT_CONSTANTS(T), + GPIO_PORT_CONSTANTS(U), + GPIO_PORT_CONSTANTS(V), + GPIO_PORT_CONSTANTS(W), + GPIO_PORT_CONSTANTS(X), + GPIO_PORT_CONSTANTS(Y), + GPIO_PORT_CONSTANTS(Z), + GPIO_PORT_CONSTANTS(AA), + GPIO_PORT_CONSTANTS(BB), + GPIO_PORT_CONSTANTS(CC), + GPIO_PORT_CONSTANTS(DD), + GPIO_PORT_CONSTANTS(EE), + GPIO_PORT_CONSTANTS(FF), + GPIO_NONE_INDEX = 0, +}; + +#define PINMUX_CONSTANTS_GPIO(name, gpio) \ + PINMUX_GPIO_##gpio = PINMUX_##name##_INDEX + +#define PINMUX_CONSTANTS(index, name, por_pu, gpio, has_gpio, \ + func0, func1, func2, func3) \ + PINMUX_##name##_INDEX = index, \ + PINMUX_##name##_FUNC_##func0 = 0, \ + PINMUX_##name##_FUNC_##func1 = 1, \ + PINMUX_##name##_FUNC_##func2 = 2, \ + PINMUX_##name##_FUNC_##func3 = 3, \ + PAD_TO_GPIO_##name = GPIO_##gpio##_INDEX, \ + PAD_HAS_GPIO_##name = has_gpio, \ + PAD_POR_PU_##name = por_pu + +#define PAD_GPIO(index, name, por_pu, gpio, func0, func1, func2, func3) \ + PINMUX_CONSTANTS(index, name, por_pu, gpio, 1, \ + func0, func1, func2, func3), \ + PINMUX_CONSTANTS_GPIO(name, gpio) + +#define PAD_NO_GPIO(index, name, por_pu, func0, func1, func2, func3) \ + PINMUX_CONSTANTS(index, name, por_pu, NONE, 0, \ + func0, func1, func2, func3) + +enum { + /* Power-on-reset pull states. */ + POR_PU = 1, + POR_PD = 0, + POR_NP = 0, + + PAD_GPIO(0, ULPI_DATA0, POR_PU, O1, SPI3, HSI, UA3, ULPI), + PAD_GPIO(1, ULPI_DATA1, POR_PU, O2, SPI3, HSI, UA3, ULPI), + PAD_GPIO(2, ULPI_DATA2, POR_PU, O3, SPI3, HSI, UA3, ULPI), + PAD_GPIO(3, ULPI_DATA3, POR_PU, O4, SPI3, HSI, UA3, ULPI), + PAD_GPIO(4, ULPI_DATA4, POR_PU, O5, SPI2, HSI, UA3, ULPI), + PAD_GPIO(5, ULPI_DATA5, POR_PU, O6, SPI2, HSI, UA3, ULPI), + PAD_GPIO(6, ULPI_DATA6, POR_PU, O7, SPI2, HSI, UA3, ULPI), + PAD_GPIO(7, ULPI_DATA7, POR_PU, O0, SPI2, HSI, UA3, ULPI), + PAD_GPIO(8, ULPI_CLK, POR_NP, Y0, SPI1, SPI5, UD3, ULPI), + PAD_GPIO(9, ULPI_DIR, POR_NP, Y1, SPI1, SPI5, UD3, ULPI), + PAD_GPIO(10, ULPI_NXT, POR_NP, Y2, SPI1, SPI5, UD3, ULPI), + PAD_GPIO(11, ULPI_STP, POR_NP, Y3, SPI1, SPI5, UD3, ULPI), + PAD_GPIO(12, DAP3_FS, POR_PD, P0, I2S2, SPI5, DCA, DCB), + PAD_GPIO(13, DAP3_DIN, POR_PD, P1, I2S2, SPI5, DCA, DCB), + PAD_GPIO(14, DAP3_DOUT, POR_PD, P2, I2S2, SPI5, DCA, RES3), + PAD_GPIO(15, DAP3_SCLK, POR_PD, P3, I2S2, SPI5, RES2, DCB), + PAD_GPIO(16, GPIO_PV0, POR_NP, V0, RES0, RES1, RES2, RES3), + PAD_GPIO(17, GPIO_PV1, POR_NP, V1, RES0, RES1, RES2, RES3), + PAD_GPIO(18, SDMMC1_CLK, POR_PD, Z0, SDMMC1, CLK12M, RES2, RES3), + PAD_GPIO(19, SDMMC1_CMD, POR_PU, Z1, SDMMC1, SPDIF, SPI4, UA3), + PAD_GPIO(20, SDMMC1_DAT3, POR_PU, Y4, SDMMC1, SPDIF, SPI4, UA3), + PAD_GPIO(21, SDMMC1_DAT2, POR_PU, Y5, SDMMC1, PWM0, SPI4, UA3), + PAD_GPIO(22, SDMMC1_DAT1, POR_PU, Y6, SDMMC1, PWM1, SPI4, UA3), + PAD_GPIO(23, SDMMC1_DAT0, POR_PU, Y7, SDMMC1, RES1, SPI4, UA3), + PAD_GPIO(26, CLK2_OUT, POR_PD, W5, EXTPERIPH2, RES1, RES2, RES3), + PAD_GPIO(27, CLK2_REQ, POR_NP, CC5, DAP, RES1, RES2, RES3), + PAD_GPIO(68, HDMI_INT, POR_PD, N7, RES0, RES1, RES2, RES3), + PAD_GPIO(69, DDC_SCL, POR_NP, V4, I2C4, RES1, RES2, RES3), + PAD_GPIO(70, DDC_SDA, POR_NP, V5, I2C4, RES1, RES2, RES3), + PAD_GPIO(89, UART2_RXD, POR_PU, C3, IR3, SPDIF, UA3, SPI4), + PAD_GPIO(90, UART2_TXD, POR_PU, C2, IR3, SPDIF, UA3, SPI4), + PAD_GPIO(91, UART2_RTS_N, POR_PU, J6, UA3, UB3, NOR, SPI4), + PAD_GPIO(92, UART2_CTS_N, POR_PU, J5, UA3, UB3, NOR, SPI4), + PAD_GPIO(93, UART3_TXD, POR_PU, W6, UC3, RES1, NOR, SPI4), + PAD_GPIO(94, UART3_RXD, POR_PU, W7, UC3, RES1, NOR, SPI4), + PAD_GPIO(95, UART3_CTS_N, POR_PU, A1, UC3, SDMMC1, DTV, NOR), + PAD_GPIO(96, UART3_RTS_N, POR_PU, C0, UC3, PWM0, DTV, NOR), + PAD_GPIO(97, GPIO_PU0, POR_NP, U0, OWR, UA3, NOR, RES3), + PAD_GPIO(98, GPIO_PU1, POR_NP, U1, RES0, UA3, NOR, RES3), + PAD_GPIO(99, GPIO_PU2, POR_NP, U2, RES0, UA3, NOR, RES3), + PAD_GPIO(100, GPIO_PU3, POR_NP, U3, PWM0, UA3, NOR, DCB), + PAD_GPIO(101, GPIO_PU4, POR_NP, U4, PWM1, UA3, NOR, DCB), + PAD_GPIO(102, GPIO_PU5, POR_NP, U5, PWM2, UA3, NOR, DCB), + PAD_GPIO(103, GPIO_PU6, POR_NP, U6, PWM3, UA3, RES2, NOR), + PAD_GPIO(104, GEN1_I2C_SDA, POR_NP, C5, I2C1, RES1, RES2, RES3), + PAD_GPIO(105, GEN1_I2C_SCL, POR_NP, C4, I2C1, RES1, RES2, RES3), + PAD_GPIO(106, DAP4_FS, POR_PD, P4, I2S3, NOR, DTV, RES3), + PAD_GPIO(107, DAP4_DIN, POR_PD, P5, I2S3, NOR, RES2, RES3), + PAD_GPIO(108, DAP4_DOUT, POR_PD, P6, I2S3, NOR, DTV, RES3), + PAD_GPIO(109, DAP4_SCLK, POR_PD, P7, I2S3, NOR, RES2, RES3), + PAD_GPIO(110, CLK3_OUT, POR_NP, EE0, EXTPERIPH3, RES1, RES2, RES3), + PAD_GPIO(111, CLK3_REQ, POR_NP, EE1, DEV3, RES1, RES2, RES3), + PAD_GPIO(112, GPIO_PC7, POR_PU, C7, RES0, RES1, NOR_WP_N, NOR_INT1), + PAD_GPIO(113, GPIO_PI5, POR_PU, I5, SDMMC2, RES1, NOR, RES3), + PAD_GPIO(114, GPIO_PI7, POR_PU, I7, RES0, TRACE, NOR, DTV), + PAD_GPIO(115, GPIO_PK0, POR_PU, K0, RES0, SDMMC3, NOR, SOC_THERM), + PAD_GPIO(116, GPIO_PK1, POR_PD, K1, SDMMC2, TRACE, NOR, RES3), + PAD_GPIO(117, GPIO_PJ0, POR_PU, J0, RES0, RES1, NOR, USB), + PAD_GPIO(118, GPIO_PJ2, POR_PU, J2, RES0, RES1, NOR, SOC_THERM), + PAD_GPIO(119, GPIO_PK3, POR_PU, K3, SDMMC2, TRACE, NOR, CCLA), + PAD_GPIO(120, GPIO_PK4, POR_PU, K4, SDMMC2, RES1, NOR_AD22, NOR_INT1), + PAD_GPIO(121, GPIO_PK2, POR_PU, K2, RES0, RES1, NOR, RES3), + PAD_GPIO(122, GPIO_PI3, POR_PU, I3, RES0, RES1, NOR, SPI4), + PAD_GPIO(123, GPIO_PI6, POR_PU, I6, RES0, RES1, NOR, SDMMC2), + PAD_GPIO(124, GPIO_PG0, POR_NP, G0, RES0, RES1, NOR, RES3), + PAD_GPIO(125, GPIO_PG1, POR_NP, G1, RES0, RES1, NOR, RES3), + PAD_GPIO(126, GPIO_PG2, POR_NP, G2, RES0, TRACE, NOR, RES3), + PAD_GPIO(127, GPIO_PG3, POR_NP, G3, RES0, TRACE, NOR, RES3), + PAD_GPIO(128, GPIO_PG4, POR_NP, G4, RES0, TMDS, NOR, SPI4), + PAD_GPIO(129, GPIO_PG5, POR_NP, G5, RES0, RES1, NOR, SPI4), + PAD_GPIO(130, GPIO_PG6, POR_NP, G6, RES0, RES1, NOR, SPI4), + PAD_GPIO(131, GPIO_PG7, POR_NP, G7, RES0, RES1, NOR, SPI4), + PAD_GPIO(132, GPIO_PH0, POR_PD, H0, PWM0, TRACE, NOR, DTV), + PAD_GPIO(133, GPIO_PH1, POR_PD, H1, PWM1, TMDS, NOR, DCA), + PAD_GPIO(134, GPIO_PH2, POR_PD, H2, PWM2, TDMS, NOR, CLDVFS), + PAD_GPIO(135, GPIO_PH3, POR_PD, H3, PWM3, SPI4, NOR, CLDVFS), + PAD_GPIO(136, GPIO_PH4, POR_PU, H4, SDMMC2, RES1, NOR, RES3), + PAD_GPIO(137, GPIO_PH5, POR_PD, H5, SDMMC2, RES1, NOR, RES3), + PAD_GPIO(138, GPIO_PH6, POR_PU, H6, SDMMC2, TRACE, NOR, DTV), + PAD_GPIO(139, GPIO_PH7, POR_PU, H7, SDMMC2, TRACE, NOR, DTV), + PAD_GPIO(140, GPIO_PJ7, POR_NP, J7, UD3, RES1, NOR_AD16, NOR_INT2), + PAD_GPIO(141, GPIO_PB0, POR_NP, B0, UD3, RES1, NOR, RES3), + PAD_GPIO(142, GPIO_PB1, POR_NP, B1, UD3, RES1, NOR, RES3), + PAD_GPIO(143, GPIO_PK7, POR_NP, K7, UD3, RES1, NOR, RES3), + PAD_GPIO(144, GPIO_PI0, POR_PU, I0, RES0, RES1, NOR, RES3), + PAD_GPIO(145, GPIO_PI1, POR_PU, I1, RES0, RES1, NOR, RES3), + PAD_GPIO(146, GPIO_PI2, POR_PU, I2, SDMMC2, TRACE, NOR, RES3), + PAD_GPIO(147, GPIO_PI4, POR_PD, I4, SPI4, TRACE, NOR, DCA), + PAD_GPIO(148, GEN2_I2C_SCL, POR_NP, T5, I2C2, RES1, NOR, RES3), + PAD_GPIO(149, GEN2_I2C_SDA, POR_NP, T6, I2C2, RES1, NOR, RES3), + PAD_GPIO(150, SDMMC4_CLK, POR_PD, CC4, SDMMC4, RES1, NOR, RES3), + PAD_GPIO(151, SDMMC4_CMD, POR_PU, T7, SDMMC4, RES1, NOR, RES3), + PAD_GPIO(152, SDMMC4_DAT0, POR_PU, AA0, SDMMC4, SPI3, NOR, RES3), + PAD_GPIO(153, SDMMC4_DAT1, POR_PU, AA1, SDMMC4, SPI3, NOR, RES3), + PAD_GPIO(154, SDMMC4_DAT2, POR_PU, AA2, SDMMC4, SPI3, NOR, RES3), + PAD_GPIO(155, SDMMC4_DAT3, POR_PU, AA3, SDMMC4, SPI3, NOR, RES3), + PAD_GPIO(156, SDMMC4_DAT4, POR_PU, AA4, SDMMC4, SPI3, NOR, RES3), + PAD_GPIO(157, SDMMC4_DAT5, POR_PU, AA5, SDMMC4, SPI3, RES2, RES3), + PAD_GPIO(158, SDMMC4_DAT6, POR_PU, AA6, SDMMC4, SPI3, NOR, RES3), + PAD_GPIO(159, SDMMC4_DAT7, POR_PU, AA7, SDMMC4, RES1, NOR, RES3), + PAD_GPIO(161, CAM_MCLK, POR_PU, CC0, VIMCLK_PRI, VIMCLK_ALT1, + VIMCLK_ALT3, SDMMC2), + PAD_GPIO(162, GPIO_PCC1, POR_PU, CC1, I2S4, RES1, RES2, SDMMC2), + PAD_GPIO(163, GPIO_PBB0, POR_PD, BB0, VGP6, VIMCLK2_PRI, SDMMC2, VIMCLK2_ALT3), + PAD_GPIO(164, CAM_I2C_SCL, POR_NP, BB1, VGP1, I2C3, RES2, SDMMC2), + PAD_GPIO(165, CAM_I2C_SDA, POR_NP, BB2, VGP2, I2C3, RES2, SDMMC2), + PAD_GPIO(166, GPIO_PBB3, POR_PD, BB3, VGP3, DCA, DCB, SDMMC2), + PAD_GPIO(167, GPIO_PBB4, POR_PD, BB4, VGP4, DCA, DCB, SDMMC2), + PAD_GPIO(168, GPIO_PBB5, POR_PD, BB5, VGP5, DCA, RES2, SDMMC2), + PAD_GPIO(169, GPIO_PBB6, POR_PD, BB6, I2S4, RES1, DCB, SDMMC2), + PAD_GPIO(170, GPIO_PBB7, POR_PD, BB7, I2S4, RES1, RES2, SDMMC2), + PAD_GPIO(171, GPIO_PCC2, POR_PU, CC2, I2S4, RES1, SDMMC3, SDMMC2), + PAD_NO_GPIO(172, JTAG_RTCK, POR_PU, RTCK, RES1, RES2, RES3), + PAD_GPIO(173, PWR_I2C_SCL, POR_NP, Z6, I2CPMU, RES1, RES2, RES3), + PAD_GPIO(174, PWR_I2C_SDA, POR_NP, Z7, I2CPMU, RES1, RES2, RES3), + PAD_GPIO(175, KB_ROW0, POR_PD, R0, RES0, RES1, RES2, RES3), + PAD_GPIO(176, KB_ROW1, POR_PD, R1, RES0, RES1, RES2, RES3), + PAD_GPIO(177, KB_ROW2, POR_PD, R2, RES0, RES1, RES2, RES3), + PAD_GPIO(178, KB_ROW3, POR_NP, R3, RES0, DCA, SYS_CLK, DCB), + PAD_GPIO(179, KB_ROW4, POR_PD, R4, RES0, DCA, RES2, DCB), + PAD_GPIO(180, KB_ROW5, POR_PD, R5, RES0, DCA, RES2, DCB), + PAD_GPIO(181, KB_ROW6, POR_PD, R6, RES0, DCA_LSC0, DCA_LSPII, DCB), + PAD_GPIO(182, KB_ROW7, POR_PD, R7, RES0, RES1, CLDVFS, UA3), + PAD_GPIO(183, KB_ROW8, POR_PD, S0, RES0, RES1, CLDVFS, UA3), + PAD_GPIO(184, KB_ROW9, POR_PD, S1, RES0, RES1, RES2, UA3), + PAD_GPIO(185, KB_ROW10, POR_PD, S2, RES0, RES1, RES2, UA3), + PAD_GPIO(186, KB_ROW11, POR_PD, S3, RES0, RES1, RES2, IR3), + PAD_GPIO(187, KB_ROW12, POR_PD, S4, RES0, RES1, RES2, IR3), + PAD_GPIO(188, KB_ROW13, POR_PD, S5, RES0, RES1, SPI2, RES3), + PAD_GPIO(189, KB_ROW14, POR_PD, S6, RES0, RES1, SPI2, RES3), + PAD_GPIO(190, KB_ROW15, POR_PD, S7, RES0, SOC_THERM, RES2, RES3), + PAD_GPIO(191, KB_COL0, POR_PU, Q0, RES0, RES1, SPI2, RES3), + PAD_GPIO(192, KB_COL1, POR_PU, Q1, RES0, RES1, SPI2, RES3), + PAD_GPIO(193, KB_COL2, POR_PU, Q2, RES0, RES1, SPI2, RES3), + PAD_GPIO(194, KB_COL3, POR_PU, Q3, RES0, DCA, PWM2, UA3), + PAD_GPIO(195, KB_COL4, POR_PU, Q4, RES0, OWR, SDMMC3, UA3), + PAD_GPIO(196, KB_COL5, POR_PU, Q5, RES0, RES1, SDMMC3, RES3), + PAD_GPIO(197, KB_COL6, POR_PU, Q6, RES0, RES1, SPI2, UD3), + PAD_GPIO(198, KB_COL7, POR_PU, Q7, RES0, RES1, SPI2, UD3), + PAD_GPIO(199, CLK_32K_OUT, POR_PD, A0, BLINK, SOC_THERM, RES2, RES3), + PAD_NO_GPIO(201, CORE_PWR_REQ, POR_NP, PWRON, RES1, RES2, RES3), + PAD_NO_GPIO(202, CPU_PWR_REQ, POR_NP, CPU, RES1, RES2, RES3), + PAD_NO_GPIO(203, PWR_INT_N, POR_NP, PMICINTR, RES1, RES2, RES3), + PAD_NO_GPIO(204, CLK_32K_IN, POR_NP, CLK_32K_IN, RES1, RES2, RES3), + PAD_NO_GPIO(205, OWR, POR_NP, OWR, RES1, RES2, RES3), + PAD_GPIO(206, DAP1_FS, POR_PD, N0, I2S0, DAP1, NOR, RES3), + PAD_GPIO(207, DAP1_DIN, POR_PD, N1, I2S0, DAP1, NOR, RES3), + PAD_GPIO(208, DAP1_DOUT, POR_PD, N2, I2S0, DAP1, NOR, SATA), + PAD_GPIO(209, DAP1_SCLK, POR_PD, N3, I2S0, DAP1, NOR, RES3), + PAD_GPIO(210, DAP_MCLK1_REQ, POR_PD, EE2, DAP, DAP1, SATA, RES3), + PAD_GPIO(211, DAP_MCLK1, POR_PD, W4, EXTPERIPH1, DAP2, RES2, RES3), + PAD_GPIO(212, SPDIF_IN, POR_PU, K6, SPDIF, RES1, RES2, I2C3), + PAD_GPIO(213, SPDIF_OUT, POR_PU, K5, SPDIF, RES1, RES2, I2C3), + PAD_GPIO(214, DAP2_FS, POR_PD, A2, I2S1, DAP2, NOR, RES3), + PAD_GPIO(215, DAP2_DIN, POR_PD, A4, I2S1, DAP2, NOR, RES3), + PAD_GPIO(216, DAP2_DOUT, POR_PD, A5, I2S1, DAP2, NOR, RES3), + PAD_GPIO(217, DAP2_SCLK, POR_PD, A3, I2S1, SAP2, NOR, RES3), + PAD_GPIO(218, DVFS_PWM, POR_PD, X0, SPI6, CLDVFS, NOR, RES3), + PAD_GPIO(219, GPIO_X1_AUD, POR_PD, X1, SPI6, RES1, NOR, RES3), + PAD_GPIO(220, GPIO_X3_AUD, POR_PU, X3, SPI6, SPI1, NOR, RES3), + PAD_GPIO(221, DVFS_CLK, POR_PU, X2, SPI6, CLDVFS_CLK, NOR, RES3), + PAD_GPIO(222, GPIO_X4_AUD, POR_PD, X4, NOR, SPI1, SPI2, DAP2), + PAD_GPIO(223, GPIO_X5_AUD, POR_PU, X5, NOR, SPI1, SPI2, RES3), + PAD_GPIO(224, GPIO_X6_AUD, POR_PU, X6, SPI6, SPI1, SPI2, NOR), + PAD_GPIO(225, GPIO_X7_AUD, POR_PD, X7, RES0, SPI1, SPI2, RES3), + PAD_GPIO(228, SDMMC3_CLK, POR_PD, A6, SDMMC3, RES1, RES2, SPI3), + PAD_GPIO(229, SDMMC3_CMD, POR_PU, A7, SDMMC3, PWM3, UA3, SPI3), + PAD_GPIO(230, SDMMC3_DAT0, POR_PU, B7, SDMMC3, RES1, RES2, SPI3), + PAD_GPIO(231, SDMMC3_DAT1, POR_PU, B6, SDMMC3, PWM2, UA3, SPI3), + PAD_GPIO(232, SDMMC3_DAT2, POR_PU, B5, SDMMC3, PWM1, DCA, SPI3), + PAD_GPIO(233, SDMMC3_DAT3, POR_PU, B4, SDMMC3, PWM0, DCB, SPI3), + PAD_GPIO(239, PEX_L0_RST_N, POR_NP, DD1, PE0, RES1, RES2, RES3), + PAD_GPIO(240, PEX_L0_CLKREQ_N, POR_NP, DD2, PE0, RES1, RES2, RES3), + PAD_GPIO(241, PEX_WAKE_N, POR_NP, DD3, PE, RES1, RES2, RES3), + PAD_GPIO(243, PEX_L1_RST_N, POR_NP, DD5, PE1, RES1, RES2, RES3), + PAD_GPIO(244, PEX_L1_CLKREQ_N, POR_NP, DD6, PE1, RES1, RES2, RES3), + PAD_GPIO(248, HDMI_CEC, POR_NP, EE3, CEC, RES1, RES2, RES3), + PAD_GPIO(249, SDMMC1_WP_N, POR_PU, V3, SDMMC1, CLK12M, SPI4, UA3), + PAD_GPIO(250, SDMMC3_CD_N, POR_PU, V2, SDMMC3, OWR, RES2, RES3), + PAD_GPIO(251, GPIO_W2_AUD, POR_PU, W2, SPI6, RES1, SPI2, I2C1), + PAD_GPIO(252, GPIO_W3_AUD, POR_PU, W3, SPI6, SPI1, SPI2, I2C1), + PAD_GPIO(253, USB_VBUS_EN0, POR_NP, N4, USB, RES1, RES2, RES3), + PAD_GPIO(254, USB_VBUS_EN1, POR_NP, N5, USB, RES1, RES2, RES3), + PAD_GPIO(255, SDMMC3_CLK_LB_IN, POR_PD, EE5, SDMMC3, RES1, RES2, RES3), + PAD_GPIO(256, SDMMC3_CLK_LB_OUT, POR_NP, EE4, SDMMC3, RES1, RES2, RES3), + PAD_NO_GPIO(258, RESET_OUT_N, POR_NP, RES0, RES1, RES2, RESET), + PAD_GPIO(259, KB_ROW16, POR_PD, T0, RES0, RES1, RES2, UC3), + PAD_GPIO(260, KB_ROW17, POR_PD, T1, RES0, RES1, RES2, UC3), + PAD_GPIO(261, USB_VBUS_EN2, POR_NP, FF1, USB, RES1, RES2, RES3), + PAD_GPIO(262, GPIO_PFF2, POR_NP, FF2, SATA, RES1, RES2, RES3), + PAD_GPIO(268, DP_HPD, POR_NP, FF0, DP, RES1, RES2, RES3), +}; + +#endif /* __SOC_NVIDIA_TEGRA132_PINMUX_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/pmc.h b/src/soc/nvidia/tegra132/include/soc/pmc.h new file mode 100644 index 0000000000..119b3be54b --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/pmc.h @@ -0,0 +1,400 @@ +/* + * Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA132_PMC_H_ +#define _TEGRA132_PMC_H_ + +#include <stdint.h> + +enum { + POWER_PARTID_CRAIL = 0, + POWER_PARTID_TD = 1, + POWER_PARTID_VE = 2, + POWER_PARTID_VDE = 4, + POWER_PARTID_L2C = 5, + POWER_PARTID_MPE = 6, + POWER_PARTID_HEG = 7, + POWER_PARTID_CE1 = 9, + POWER_PARTID_CE2 = 10, + POWER_PARTID_CE3 = 11, + POWER_PARTID_CELP = 12, + POWER_PARTID_CE0 = 14, + POWER_PARTID_C0NC = 15, + POWER_PARTID_C1NC = 16, + POWER_PARTID_SOR = 17, + POWER_PARTID_DIS = 18, + POWER_PARTID_DISB = 19, + POWER_PARTID_XUSBA = 20, + POWER_PARTID_XUSBB = 21, + POWER_PARTID_XUSBC = 22 +}; + +struct tegra_pmc_regs { + u32 cntrl; + u32 sec_disable; + u32 pmc_swrst; + u32 wake_mask; + u32 wake_lvl; + u32 wake_status; + u32 sw_wake_status; + u32 dpd_pads_oride; + u32 dpd_sample; + u32 dpd_enable; + u32 pwrgate_timer_off; + u32 clamp_status; + u32 pwrgate_toggle; + u32 remove_clamping_cmd; + u32 pwrgate_status; + u32 pwrgood_timer; + u32 blink_timer; + u32 no_iopower; + u32 pwr_det; + u32 pwr_det_latch; + u32 scratch0; + u32 scratch1; + u32 scratch2; + u32 scratch3; + u32 scratch4; + u32 scratch5; + u32 scratch6; + u32 scratch7; + u32 scratch8; + u32 scratch9; + u32 scratch10; + u32 scratch11; + u32 scratch12; + u32 scratch13; + u32 scratch14; + u32 scratch15; + u32 scratch16; + u32 scratch17; + u32 scratch18; + u32 scratch19; + u32 odmdata; + u32 scratch21; + u32 scratch22; + u32 scratch23; + u32 secure_scratch0; + u32 secure_scratch1; + u32 secure_scratch2; + u32 secure_scratch3; + u32 secure_scratch4; + u32 secure_scratch5; + u32 cpupwrgood_timer; + u32 cpupwroff_timer; + u32 pg_mask; + u32 pg_mask_1; + u32 auto_wake_lvl; + u32 auto_wake_lvl_mask; + u32 wake_delay; + u32 pwr_det_val; + u32 ddr_pwr; + u32 usb_debounce_del; + u32 usb_a0; + u32 crypto_op; + u32 pllp_wb0_override; + u32 scratch24; + u32 scratch25; + u32 scratch26; + u32 scratch27; + u32 scratch28; + u32 scratch29; + u32 scratch30; + u32 scratch31; + u32 scratch32; + u32 scratch33; + u32 scratch34; + u32 scratch35; + u32 scratch36; + u32 scratch37; + u32 scratch38; + u32 scratch39; + u32 scratch40; + u32 scratch41; + u32 scratch42; + u32 bondout_mirror[3]; + u32 sys_33v_en; + u32 bondout_mirror_access; + u32 gate; + u32 wake2_mask; + u32 wake2_lvl; + u32 wake2_status; + u32 sw_wake2_status; + u32 auto_wake2_lvl_mask; + u32 pg_mask_2; + u32 pg_mask_ce1; + u32 pg_mask_ce2; + u32 pg_mask_ce3; + u32 pwrgate_timer_ce[7]; + u32 pcx_edpd_cntrl; + u32 osc_edpd_over; + u32 clk_out_cntrl; + u32 sata_pwrgt; + u32 sensor_ctrl; + u32 rst_status; + u32 io_dpd_req; + u32 io_dpd_status; + u32 io_dpd2_req; + u32 io_dpd2_status; + u32 sel_dpd_tim; + u32 vddp_sel; + u32 ddr_cfg; + u32 e_no_vttgen; + u8 _rsv0[4]; + u32 pllm_wb0_override_freq; + u32 test_pwrgate; + u32 pwrgate_timer_mult; + u32 dis_sel_dpd; + u32 utmip_uhsic_triggers; + u32 utmip_uhsic_saved_state; + u32 utmip_pad_cfg; + u32 utmip_term_pad_cfg; + u32 utmip_uhsic_sleep_cfg; + u32 utmip_uhsic_sleepwalk_cfg; + u32 utmip_sleepwalk_p[3]; + u32 uhsic_sleepwalk_p0; + u32 utmip_uhsic_status; + u32 utmip_uhsic_fake; + u32 bondout_mirror3[5 - 3]; + u32 secure_scratch6; + u32 secure_scratch7; + u32 scratch43; + u32 scratch44; + u32 scratch45; + u32 scratch46; + u32 scratch47; + u32 scratch48; + u32 scratch49; + u32 scratch50; + u32 scratch51; + u32 scratch52; + u32 scratch53; + u32 scratch54; + u32 scratch55; + u32 scratch0_eco; + u32 por_dpd_ctrl; + u32 scratch2_eco; + u32 utmip_uhsic_line_wakeup; + u32 utmip_bias_master_cntrl; + u32 utmip_master_config; + u32 td_pwrgate_inter_part_timer; + u32 utmip_uhsic2_triggers; + u32 utmip_uhsic2_saved_state; + u32 utmip_uhsic2_sleep_cfg; + u32 utmip_uhsic2_sleepwalk_cfg; + u32 uhsic2_sleepwalk_p1; + u32 utmip_uhsic2_status; + u32 utmip_uhsic2_fake; + u32 utmip_uhsic2_line_wakeup; + u32 utmip_master2_config; + u32 utmip_uhsic_rpd_cfg; + u32 pg_mask_ce0; + u32 pg_mask3[5 - 3]; + u32 pllm_wb0_override2; + u32 tsc_mult; + u32 cpu_vsense_override; + u32 glb_amap_cfg; + u32 sticky_bits; + u32 sec_disable2; + u32 weak_bias; + u32 reg_short; + u32 pg_mask_andor; + u8 _rsv1[0x2c]; + u32 secure_scratch8; + u32 secure_scratch9; + u32 secure_scratch10; + u32 secure_scratch11; + u32 secure_scratch12; + u32 secure_scratch13; + u32 secure_scratch14; + u32 secure_scratch15; + u32 secure_scratch16; + u32 secure_scratch17; + u32 secure_scratch18; + u32 secure_scratch19; + u32 secure_scratch20; + u32 secure_scratch21; + u32 secure_scratch22; + u32 secure_scratch23; + u32 secure_scratch24; + u32 secure_scratch25; + u32 secure_scratch26; + u32 secure_scratch27; + u32 secure_scratch28; + u32 secure_scratch29; + u32 secure_scratch30; + u32 secure_scratch31; + u32 secure_scratch32; + u32 secure_scratch33; + u32 secure_scratch34; + u32 secure_scratch35; + u8 _rsv2[0xd0]; + u32 cntrl2; + u8 _rsv3[0x18]; + u32 io_dpd3_req; + u32 io_dqd3_status; + u32 strapping_opt_a; + u8 _rsv4[0x198]; + u32 scratch56; + u32 scratch57; + u32 scratch58; + u32 scratch59; + u32 scratch60; + u32 scratch61; + u32 scratch62; + u32 scratch63; + u32 scratch64; + u32 scratch65; + u32 scratch66; + u32 scratch67; + u32 scratch68; + u32 scratch69; + u32 scratch70; + u32 scratch71; + u32 scratch72; + u32 scratch73; + u32 scratch74; + u32 scratch75; + u32 scratch76; + u32 scratch77; + u32 scratch78; + u32 scratch79; + u32 scratch80; + u32 scratch81; + u32 scratch82; + u32 scratch83; + u32 scratch84; + u32 scratch85; + u32 scratch86; + u32 scratch87; + u32 scratch88; + u32 scratch89; + u32 scratch90; + u32 scratch91; + u32 scratch92; + u32 scratch93; + u32 scratch94; + u32 scratch95; + u32 scratch96; + u32 scratch97; + u32 scratch98; + u32 scratch99; + u32 scratch100; + u32 scratch101; + u32 scratch102; + u32 scratch103; + u32 scratch104; + u32 scratch105; + u32 scratch106; + u32 scratch107; + u32 scratch108; + u32 scratch109; + u32 scratch110; + u32 scratch111; + u32 scratch112; + u32 scratch113; + u32 scratch114; + u32 scratch115; + u32 scratch116; + u32 scratch117; + u32 scratch118; + u32 scratch119; +}; + +check_member(tegra_pmc_regs, scratch119, 0x6fc); + +enum { + PMC_RST_STATUS_SOURCE_MASK = 0x7, + PMC_RST_STATUS_SOURCE_POR = 0x0, + PMC_RST_STATUS_SOURCE_WATCHDOG = 0x1, + PMC_RST_STATUS_SOURCE_SENSOR = 0x2, + PMC_RST_STATUS_SOURCE_SW_MAIN = 0x3, + PMC_RST_STATUS_SOURCE_LP0 = 0x4, + PMC_RST_STATUS_NUM_SOURCES = 0x5, +}; + +enum { + PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f, + PMC_PWRGATE_TOGGLE_PARTID_SHIFT = 0, + PMC_PWRGATE_TOGGLE_START = 0x1 << 8 +}; + +enum { + PMC_CNTRL_KBC_CLK_DIS = 0x1 << 0, + PMC_CNTRL_RTC_CLK_DIS = 0x1 << 1, + PMC_CNTRL_RTC_RST = 0x1 << 2, + PMC_CNTRL_KBC_RST = 0x1 << 3, + PMC_CNTRL_MAIN_RST = 0x1 << 4, + PMC_CNTRL_LATCHWAKE_EN = 0x1 << 5, + PMC_CNTRL_GLITCHDET_DIS = 0x1 << 6, + PMC_CNTRL_BLINK_EN = 0x1 << 7, + PMC_CNTRL_PWRREQ_POLARITY = 0x1 << 8, + PMC_CNTRL_PWRREQ_OE = 0x1 << 9, + PMC_CNTRL_SYSCLK_POLARITY = 0x1 << 10, + PMC_CNTRL_SYSCLK_OE = 0x1 << 11, + PMC_CNTRL_PWRGATE_DIS = 0x1 << 12, + PMC_CNTRL_AOINIT = 0x1 << 13, + PMC_CNTRL_SIDE_EFFECT_LP0 = 0x1 << 14, + PMC_CNTRL_CPUPWRREQ_POLARITY = 0x1 << 15, + PMC_CNTRL_CPUPWRREQ_OE = 0x1 << 16, + PMC_CNTRL_INTR_POLARITY = 0x1 << 17, + PMC_CNTRL_FUSE_OVERRIDE = 0x1 << 18, + PMC_CNTRL_CPUPWRGOOD_EN = 0x1 << 19, + PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT = 20, + PMC_CNTRL_CPUPWRGOOD_SEL_MASK = + 0x3 << PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT +}; + +enum { + PMC_DDR_PWR_EMMC_MASK = 1 << 1, + PMC_DDR_PWR_VAL_MASK = 1 << 0, +}; + +enum { + PMC_DDR_CFG_PKG_MASK = 1 << 0, + PMC_DDR_CFG_IF_MASK = 1 << 1, + PMC_DDR_CFG_XM0_RESET_TRI_MASK = 1 << 12, + PMC_DDR_CFG_XM0_RESET_DPDIO_MASK = 1 << 13, +}; + +enum { + PMC_NO_IOPOWER_MEM_MASK = 1 << 7, + PMC_NO_IOPOWER_MEM_COMP_MASK = 1 << 16, +}; + +enum { + PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK = 1 << 0, + PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK = 1 << 1, + PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK = 1 << 31, +}; + +enum { + PMC_CNTRL2_HOLD_CKE_LOW_EN = 0x1 << 12 +}; + +enum { + PMC_OSC_EDPD_OVER_XOFS_SHIFT = 1, + PMC_OSC_EDPD_OVER_XOFS_MASK = + 0x3f << PMC_OSC_EDPD_OVER_XOFS_SHIFT +}; + +enum { + PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT = 4, + PMC_STRAPPING_OPT_A_RAM_CODE_MASK = + 0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT, +}; + +#endif /* _TEGRA132_PMC_H_ */ diff --git a/src/soc/nvidia/tegra132/include/soc/power.h b/src/soc/nvidia/tegra132/include/soc/power.h new file mode 100644 index 0000000000..d42116eb75 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/power.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_POWER_H__ +#define __SOC_NVIDIA_TEGRA132_POWER_H__ + +#include <soc/pmc.h> + +void power_ungate_partition(uint32_t id); + +uint8_t pmc_rst_status(void); +void pmc_print_rst_status(void); + +#endif /* __SOC_NVIDIA_TEGRA132_POWER_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/sdram.h b/src/soc/nvidia/tegra132/include/soc/sdram.h new file mode 100644 index 0000000000..1e6e70de8c --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/sdram.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_SDRAM_H__ +#define __SOC_NVIDIA_TEGRA132_SDRAM_H__ + +#include <soc/sdram_param.h> + +uint32_t sdram_get_ram_code(void); +void sdram_init(const struct sdram_params *param); + +/* Save params to PMC scratch registers for use by BootROM on LP0 resume. */ +void sdram_lp0_save_params(const struct sdram_params *sdram); + +#endif /* __SOC_NVIDIA_TEGRA132_SDRAM_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/sdram_configs.h b/src/soc/nvidia/tegra132/include/soc/sdram_configs.h index 300be1093c..38368fb69b 100644 --- a/src/soc/nvidia/tegra132/include/soc/sdram_configs.h +++ b/src/soc/nvidia/tegra132/include/soc/sdram_configs.h @@ -20,7 +20,7 @@ #ifndef __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__ #define __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__ -#include <soc/nvidia/tegra132/sdram.h> +#include <soc/sdram.h> /* Loads SDRAM configurations for current system. */ const struct sdram_params *get_sdram_config(void); diff --git a/src/soc/nvidia/tegra132/include/soc/sdram_param.h b/src/soc/nvidia/tegra132/include/soc/sdram_param.h new file mode 100644 index 0000000000..7688930c9a --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/sdram_param.h @@ -0,0 +1,821 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. The field names are in camel case to ease + * directly converting BCT config files (*.cfg) into C structure. + */ + +#ifndef __SOC_NVIDIA_TEGRA132_SDRAM_PARAM_H__ +#define __SOC_NVIDIA_TEGRA132_SDRAM_PARAM_H__ + +#include <stddef.h> +#include <stdint.h> + +enum { + /* Specifies the memory type to be undefined */ + NvBootMemoryType_None = 0, + + /* Specifies the memory type to be DDR SDRAM */ + NvBootMemoryType_Ddr = 0, + + /* Specifies the memory type to be LPDDR SDRAM */ + NvBootMemoryType_LpDdr = 0, + + /* Specifies the memory type to be DDR2 SDRAM */ + NvBootMemoryType_Ddr2 = 0, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + NvBootMemoryType_LpDdr2, + + /* Specifies the memory type to be DDR3 SDRAM */ + NvBootMemoryType_Ddr3, + + NvBootMemoryType_Num, + + /* Specifies an entry in the ram_code table that's not in use */ + NvBootMemoryType_Unused = 0X7FFFFFF, +}; + +enum { + BOOT_ROM_PATCH_CONTROL_ENABLE_MASK = 0x1 << 31, + BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT = 0, + BOOT_ROM_PATCH_CONTROL_OFFSET_MASK = 0x7FFFFFFF << 0, + BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS = 0x70000000, + + EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK = 1 << 0, +}; + +/** + * Defines the SDRAM parameter structure + */ +struct sdram_params { + + /* Specifies the type of memory device */ + uint32_t MemoryType; + + /* MC/EMC clock source configuration */ + + /* Specifies the M value for PllM */ + uint32_t PllMInputDivider; + /* Specifies the N value for PllM */ + uint32_t PllMFeedbackDivider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + uint32_t PllMStableTime; + /* Specifies misc. control bits */ + uint32_t PllMSetupControl; + /* Enables the Div by 2 */ + uint32_t PllMSelectDiv2; + /* Powers down VCO output Level shifter */ + uint32_t PllMPDLshiftPh45; + /* Powers down VCO output Level shifter */ + uint32_t PllMPDLshiftPh90; + /* Powers down VCO output Level shifter */ + uint32_t PllMPDLshiftPh135; + /* Specifies value for Charge Pump Gain Control */ + uint32_t PllMKCP; + /* Specifies VCO gain */ + uint32_t PllMKVCO; + /* Spare BCT param */ + uint32_t EmcBctSpare0; + /* Spare BCT param */ + uint32_t EmcBctSpare1; + /* Spare BCT param */ + uint32_t EmcBctSpare2; + /* Spare BCT param */ + uint32_t EmcBctSpare3; + /* Spare BCT param */ + uint32_t EmcBctSpare4; + /* Spare BCT param */ + uint32_t EmcBctSpare5; + /* Spare BCT param */ + uint32_t EmcBctSpare6; + /* Spare BCT param */ + uint32_t EmcBctSpare7; + /* Spare BCT param */ + uint32_t EmcBctSpare8; + /* Spare BCT param */ + uint32_t EmcBctSpare9; + /* Spare BCT param */ + uint32_t EmcBctSpare10; + /* Spare BCT param */ + uint32_t EmcBctSpare11; + /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ + uint32_t EmcClockSource; + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + uint32_t EmcAutoCalInterval; + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + uint32_t EmcAutoCalConfig; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ + uint32_t EmcAutoCalConfig2; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ + uint32_t EmcAutoCalConfig3; + + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + uint32_t EmcAutoCalWait; + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + uint32_t EmcAdrCfg; + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + uint32_t EmcPinProgramWait; + /* Specifies the extra delay before/after pin RESET/CKE command */ + uint32_t EmcPinExtraWait; + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + uint32_t EmcTimingControlWait; + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + uint32_t EmcRc; + /* Specifies the value for EMC_RFC */ + uint32_t EmcRfc; + /* Specifies the value for EMC_RFC_SLR */ + uint32_t EmcRfcSlr; + /* Specifies the value for EMC_RAS */ + uint32_t EmcRas; + /* Specifies the value for EMC_RP */ + uint32_t EmcRp; + /* Specifies the value for EMC_R2R */ + uint32_t EmcR2r; + /* Specifies the value for EMC_W2W */ + uint32_t EmcW2w; + /* Specifies the value for EMC_R2W */ + uint32_t EmcR2w; + /* Specifies the value for EMC_W2R */ + uint32_t EmcW2r; + /* Specifies the value for EMC_R2P */ + uint32_t EmcR2p; + /* Specifies the value for EMC_W2P */ + uint32_t EmcW2p; + /* Specifies the value for EMC_RD_RCD */ + uint32_t EmcRdRcd; + /* Specifies the value for EMC_WR_RCD */ + uint32_t EmcWrRcd; + /* Specifies the value for EMC_RRD */ + uint32_t EmcRrd; + /* Specifies the value for EMC_REXT */ + uint32_t EmcRext; + /* Specifies the value for EMC_WEXT */ + uint32_t EmcWext; + /* Specifies the value for EMC_WDV */ + uint32_t EmcWdv; + /* Specifies the value for EMC_WDV_MASK */ + uint32_t EmcWdvMask; + /* Specifies the value for EMC_QUSE */ + uint32_t EmcQUse; + /* Specifies the value for EMC_QUSE_WIDTH */ + uint32_t EmcQuseWidth; + /* Specifies the value for EMC_IBDLY */ + uint32_t EmcIbdly; + /* Specifies the value for EMC_EINPUT */ + uint32_t EmcEInput; + /* Specifies the value for EMC_EINPUT_DURATION */ + uint32_t EmcEInputDuration; + /* Specifies the value for EMC_PUTERM_EXTRA */ + uint32_t EmcPutermExtra; + /* Specifies the value for EMC_PUTERM_WIDTH */ + uint32_t EmcPutermWidth; + /* Specifies the value for EMC_PUTERM_ADJ */ + uint32_t EmcPutermAdj; + /* Specifies the value for EMC_CDB_CNTL_1 */ + uint32_t EmcCdbCntl1; + /* Specifies the value for EMC_CDB_CNTL_2 */ + uint32_t EmcCdbCntl2; + /* Specifies the value for EMC_CDB_CNTL_3 */ + uint32_t EmcCdbCntl3; + /* Specifies the value for EMC_QRST */ + uint32_t EmcQRst; + /* Specifies the value for EMC_QSAFE */ + uint32_t EmcQSafe; + /* Specifies the value for EMC_RDV */ + uint32_t EmcRdv; + /* Specifies the value for EMC_RDV_MASK */ + uint32_t EmcRdvMask; + /* Specifies the value for EMC_QPOP */ + uint32_t EmcQpop; + /* Specifies the value for EMC_CTT */ + uint32_t EmcCtt; + /* Specifies the value for EMC_CTT_DURATION */ + uint32_t EmcCttDuration; + /* Specifies the value for EMC_REFRESH */ + uint32_t EmcRefresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + uint32_t EmcBurstRefreshNum; + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + uint32_t EmcPreRefreshReqCnt; + /* Specifies the value for EMC_PDEX2WR */ + uint32_t EmcPdEx2Wr; + /* Specifies the value for EMC_PDEX2RD */ + uint32_t EmcPdEx2Rd; + /* Specifies the value for EMC_PCHG2PDEN */ + uint32_t EmcPChg2Pden; + /* Specifies the value for EMC_ACT2PDEN */ + uint32_t EmcAct2Pden; + /* Specifies the value for EMC_AR2PDEN */ + uint32_t EmcAr2Pden; + /* Specifies the value for EMC_RW2PDEN */ + uint32_t EmcRw2Pden; + /* Specifies the value for EMC_TXSR */ + uint32_t EmcTxsr; + /* Specifies the value for EMC_TXSRDLL */ + uint32_t EmcTxsrDll; + /* Specifies the value for EMC_TCKE */ + uint32_t EmcTcke; + /* Specifies the value for EMC_TCKESR */ + uint32_t EmcTckesr; + /* Specifies the value for EMC_TPD */ + uint32_t EmcTpd; + /* Specifies the value for EMC_TFAW */ + uint32_t EmcTfaw; + /* Specifies the value for EMC_TRPAB */ + uint32_t EmcTrpab; + /* Specifies the value for EMC_TCLKSTABLE */ + uint32_t EmcTClkStable; + /* Specifies the value for EMC_TCLKSTOP */ + uint32_t EmcTClkStop; + /* Specifies the value for EMC_TREFBW */ + uint32_t EmcTRefBw; + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + uint32_t EmcFbioCfg5; + /* Specifies the value for EMC_FBIO_CFG6 */ + uint32_t EmcFbioCfg6; + /* Specifies the value for EMC_FBIO_SPARE */ + uint32_t EmcFbioSpare; + + /* Specifies the value for EMC_CFG_RSV */ + uint32_t EmcCfgRsv; + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + uint32_t EmcMrs; + /* Specifies the MP0 command to initialize mode registers */ + uint32_t EmcEmrs; + /* Specifies the MP2 command to initialize mode registers */ + uint32_t EmcEmrs2; + /* Specifies the MP3 command to initialize mode registers */ + uint32_t EmcEmrs3; + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + uint32_t EmcMrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + uint32_t EmcMrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + uint32_t EmcMrw3; + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + uint32_t EmcMrw4; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + uint32_t EmcMrwExtra; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + uint32_t EmcWarmBootMrwExtra; + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + uint32_t EmcWarmBootExtraModeRegWriteEnable; + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + uint32_t EmcExtraModeRegWriteEnable; + + /* Specifies the EMC_MRW reset command value */ + uint32_t EmcMrwResetCommand; + /* Specifies the EMC Reset wait time (in microseconds) */ + uint32_t EmcMrwResetNInitWait; + /* Specifies the value for EMC_MRS_WAIT_CNT */ + uint32_t EmcMrsWaitCnt; + /* Specifies the value for EMC_MRS_WAIT_CNT2 */ + uint32_t EmcMrsWaitCnt2; + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + uint32_t EmcCfg; + /* Specifies the value for EMC_CFG_2 */ + uint32_t EmcCfg2; + /* Specifies the pipe bypass controls */ + uint32_t EmcCfgPipe; + /* Specifies the value for EMC_DBG */ + uint32_t EmcDbg; + /* Specifies the value for EMC_CMDQ */ + uint32_t EmcCmdQ; + /* Specifies the value for EMC_MC2EMCQ */ + uint32_t EmcMc2EmcQ; + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + uint32_t EmcDynSelfRefControl; + + /* Specifies the value for MEM_INIT_DONE */ + uint32_t AhbArbitrationXbarCtrlMemInitDone; + + /* Specifies the value for EMC_CFG_DIG_DLL */ + uint32_t EmcCfgDigDll; + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + uint32_t EmcCfgDigDllPeriod; + /* Specifies the value of *DEV_SELECTN of various EMC registers */ + uint32_t EmcDevSelect; + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + uint32_t EmcSelDpdCtrl; + + /* Pads trimmer delays */ + + /* Specifies the value for EMC_DLL_XFORM_DQS0 */ + uint32_t EmcDllXformDqs0; + /* Specifies the value for EMC_DLL_XFORM_DQS1 */ + uint32_t EmcDllXformDqs1; + /* Specifies the value for EMC_DLL_XFORM_DQS2 */ + uint32_t EmcDllXformDqs2; + /* Specifies the value for EMC_DLL_XFORM_DQS3 */ + uint32_t EmcDllXformDqs3; + /* Specifies the value for EMC_DLL_XFORM_DQS4 */ + uint32_t EmcDllXformDqs4; + /* Specifies the value for EMC_DLL_XFORM_DQS5 */ + uint32_t EmcDllXformDqs5; + /* Specifies the value for EMC_DLL_XFORM_DQS6 */ + uint32_t EmcDllXformDqs6; + /* Specifies the value for EMC_DLL_XFORM_DQS7 */ + uint32_t EmcDllXformDqs7; + /* Specifies the value for EMC_DLL_XFORM_DQS8 */ + uint32_t EmcDllXformDqs8; + /* Specifies the value for EMC_DLL_XFORM_DQS9 */ + uint32_t EmcDllXformDqs9; + /* Specifies the value for EMC_DLL_XFORM_DQS10 */ + uint32_t EmcDllXformDqs10; + /* Specifies the value for EMC_DLL_XFORM_DQS11 */ + uint32_t EmcDllXformDqs11; + /* Specifies the value for EMC_DLL_XFORM_DQS12 */ + uint32_t EmcDllXformDqs12; + /* Specifies the value for EMC_DLL_XFORM_DQS13 */ + uint32_t EmcDllXformDqs13; + /* Specifies the value for EMC_DLL_XFORM_DQS14 */ + uint32_t EmcDllXformDqs14; + /* Specifies the value for EMC_DLL_XFORM_DQS15 */ + uint32_t EmcDllXformDqs15; + /* Specifies the value for EMC_DLL_XFORM_QUSE0 */ + uint32_t EmcDllXformQUse0; + /* Specifies the value for EMC_DLL_XFORM_QUSE1 */ + uint32_t EmcDllXformQUse1; + /* Specifies the value for EMC_DLL_XFORM_QUSE2 */ + uint32_t EmcDllXformQUse2; + /* Specifies the value for EMC_DLL_XFORM_QUSE3 */ + uint32_t EmcDllXformQUse3; + /* Specifies the value for EMC_DLL_XFORM_QUSE4 */ + uint32_t EmcDllXformQUse4; + /* Specifies the value for EMC_DLL_XFORM_QUSE5 */ + uint32_t EmcDllXformQUse5; + /* Specifies the value for EMC_DLL_XFORM_QUSE6 */ + uint32_t EmcDllXformQUse6; + /* Specifies the value for EMC_DLL_XFORM_QUSE7 */ + uint32_t EmcDllXformQUse7; + /* Specifies the value for EMC_DLL_XFORM_ADDR0 */ + uint32_t EmcDllXformAddr0; + /* Specifies the value for EMC_DLL_XFORM_ADDR1 */ + uint32_t EmcDllXformAddr1; + /* Specifies the value for EMC_DLL_XFORM_ADDR2 */ + uint32_t EmcDllXformAddr2; + /* Specifies the value for EMC_DLL_XFORM_ADDR3 */ + uint32_t EmcDllXformAddr3; + /* Specifies the value for EMC_DLL_XFORM_ADDR4 */ + uint32_t EmcDllXformAddr4; + /* Specifies the value for EMC_DLL_XFORM_ADDR5 */ + uint32_t EmcDllXformAddr5; + /* Specifies the value for EMC_DLL_XFORM_QUSE8 */ + uint32_t EmcDllXformQUse8; + /* Specifies the value for EMC_DLL_XFORM_QUSE9 */ + uint32_t EmcDllXformQUse9; + /* Specifies the value for EMC_DLL_XFORM_QUSE10 */ + uint32_t EmcDllXformQUse10; + /* Specifies the value for EMC_DLL_XFORM_QUSE11 */ + uint32_t EmcDllXformQUse11; + /* Specifies the value for EMC_DLL_XFORM_QUSE12 */ + uint32_t EmcDllXformQUse12; + /* Specifies the value for EMC_DLL_XFORM_QUSE13 */ + uint32_t EmcDllXformQUse13; + /* Specifies the value for EMC_DLL_XFORM_QUSE14 */ + uint32_t EmcDllXformQUse14; + /* Specifies the value for EMC_DLL_XFORM_QUSE15 */ + uint32_t EmcDllXformQUse15; + /* Specifies the value for EMC_DLI_TRIM_TXDQS0 */ + uint32_t EmcDliTrimTxDqs0; + /* Specifies the value for EMC_DLI_TRIM_TXDQS1 */ + uint32_t EmcDliTrimTxDqs1; + /* Specifies the value for EMC_DLI_TRIM_TXDQS2 */ + uint32_t EmcDliTrimTxDqs2; + /* Specifies the value for EMC_DLI_TRIM_TXDQS3 */ + uint32_t EmcDliTrimTxDqs3; + /* Specifies the value for EMC_DLI_TRIM_TXDQS4 */ + uint32_t EmcDliTrimTxDqs4; + /* Specifies the value for EMC_DLI_TRIM_TXDQS5 */ + uint32_t EmcDliTrimTxDqs5; + /* Specifies the value for EMC_DLI_TRIM_TXDQS6 */ + uint32_t EmcDliTrimTxDqs6; + /* Specifies the value for EMC_DLI_TRIM_TXDQS7 */ + uint32_t EmcDliTrimTxDqs7; + /* Specifies the value for EMC_DLI_TRIM_TXDQS8 */ + uint32_t EmcDliTrimTxDqs8; + /* Specifies the value for EMC_DLI_TRIM_TXDQS9 */ + uint32_t EmcDliTrimTxDqs9; + /* Specifies the value for EMC_DLI_TRIM_TXDQS10 */ + uint32_t EmcDliTrimTxDqs10; + /* Specifies the value for EMC_DLI_TRIM_TXDQS11 */ + uint32_t EmcDliTrimTxDqs11; + /* Specifies the value for EMC_DLI_TRIM_TXDQS12 */ + uint32_t EmcDliTrimTxDqs12; + /* Specifies the value for EMC_DLI_TRIM_TXDQS13 */ + uint32_t EmcDliTrimTxDqs13; + /* Specifies the value for EMC_DLI_TRIM_TXDQS14 */ + uint32_t EmcDliTrimTxDqs14; + /* Specifies the value for EMC_DLI_TRIM_TXDQS15 */ + uint32_t EmcDliTrimTxDqs15; + /* Specifies the value for EMC_DLL_XFORM_DQ0 */ + uint32_t EmcDllXformDq0; + /* Specifies the value for EMC_DLL_XFORM_DQ1 */ + uint32_t EmcDllXformDq1; + /* Specifies the value for EMC_DLL_XFORM_DQ2 */ + uint32_t EmcDllXformDq2; + /* Specifies the value for EMC_DLL_XFORM_DQ3 */ + uint32_t EmcDllXformDq3; + /* Specifies the value for EMC_DLL_XFORM_DQ4 */ + uint32_t EmcDllXformDq4; + /* Specifies the value for EMC_DLL_XFORM_DQ5 */ + uint32_t EmcDllXformDq5; + /* Specifies the value for EMC_DLL_XFORM_DQ6 */ + uint32_t EmcDllXformDq6; + /* Specifies the value for EMC_DLL_XFORM_DQ7 */ + uint32_t EmcDllXformDq7; + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + uint32_t WarmBootWait; + + /* Specifies the value for EMC_CTT_TERM_CTRL */ + uint32_t EmcCttTermCtrl; + + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t EmcOdtWrite; + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t EmcOdtRead; + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + uint32_t EmcZcalInterval; + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + uint32_t EmcZcalWaitCnt; + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + uint32_t EmcZcalMrwCmd; + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + uint32_t EmcMrsResetDll; + /* Specifies the command for ZQ initialization of device 0 */ + uint32_t EmcZcalInitDev0; + /* Specifies the command for ZQ initialization of device 1 */ + uint32_t EmcZcalInitDev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + uint32_t EmcZcalInitWait; + /* + * Specifies the enable for ZQ calibration at cold boot [bit 0] + * and warm boot [bit 1] + */ + uint32_t EmcZcalWarmColdBootEnables; + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + * on warmboot + */ + /* Is issued to both devices separately */ + uint32_t EmcMrwLpddr2ZcalWarmBoot; + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + uint32_t EmcZqCalDdr3WarmBoot; + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + uint32_t EmcZcalWarmBootWait; + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + uint32_t EmcMrsWarmBootEnable; + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + uint32_t EmcMrsResetDllWait; + /* Specifies the extra MRS command to initialize mode registers */ + uint32_t EmcMrsExtra; + /* Specifies the extra MRS command at warm boot */ + uint32_t EmcWarmBootMrsExtra; + /* Specifies the EMRS command to enable the DDR2 DLL */ + uint32_t EmcEmrsDdr2DllEnable; + /* Specifies the MRS command to reset the DDR2 DLL */ + uint32_t EmcMrsDdr2DllReset; + /* Specifies the EMRS command to set OCD calibration */ + uint32_t EmcEmrsDdr2OcdCalib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + uint32_t EmcDdr2Wait; + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + uint32_t EmcClkenOverride; + /* Specifies the value for MC_DIS_EXTRA_SNAP_LEVELS */ + uint32_t McDisExtraSnapLevels; + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + uint32_t EmcExtraRefreshNum; + /* Specifies the master override for all EMC clocks */ + uint32_t EmcClkenOverrideAllWarmBoot; + /* Specifies the master override for all MC clocks */ + uint32_t McClkenOverrideAllWarmBoot; + /* Specifies digital dll period, choosing between 4 to 64 ms */ + uint32_t EmcCfgDigDllPeriodWarmBoot; + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + uint32_t PmcVddpSel; + /* Specifies the wait time after programming PMC_VDDP_SEL */ + uint32_t PmcVddpSelWait; + /* Specifies the value for PMC_DDR_PWR */ + uint32_t PmcDdrPwr; + /* Specifies the value for PMC_DDR_CFG */ + uint32_t PmcDdrCfg; + /* Specifies the value for PMC_IO_DPD3_REQ */ + uint32_t PmcIoDpd3Req; + /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ + uint32_t PmcIoDpd3ReqWait; + /* Specifies the value for PMC_REG_SHORT */ + uint32_t PmcRegShort; + /* Specifies the value for PMC_NO_IOPOWER */ + uint32_t PmcNoIoPower; + /* Specifies the wait time after programming PMC_POR_DPD_CTRL */ + uint32_t PmcPorDpdCtrlWait; + /* Specifies the value for EMC_XM2CMDPADCTRL */ + uint32_t EmcXm2CmdPadCtrl; + /* Specifies the value for EMC_XM2CMDPADCTRL2 */ + uint32_t EmcXm2CmdPadCtrl2; + /* Specifies the value for EMC_XM2CMDPADCTRL3 */ + uint32_t EmcXm2CmdPadCtrl3; + /* Specifies the value for EMC_XM2CMDPADCTRL4 */ + uint32_t EmcXm2CmdPadCtrl4; + /* Specifies the value for EMC_XM2CMDPADCTRL5 */ + uint32_t EmcXm2CmdPadCtrl5; + /* Specifies the value for EMC_XM2DQSPADCTRL */ + uint32_t EmcXm2DqsPadCtrl; + /* Specifies the value for EMC_XM2DQSPADCTRL2 */ + uint32_t EmcXm2DqsPadCtrl2; + /* Specifies the value for EMC_XM2DQSPADCTRL3 */ + uint32_t EmcXm2DqsPadCtrl3; + /* Specifies the value for EMC_XM2DQSPADCTRL4 */ + uint32_t EmcXm2DqsPadCtrl4; + /* Specifies the value for EMC_XM2DQSPADCTRL5 */ + uint32_t EmcXm2DqsPadCtrl5; + /* Specifies the value for EMC_XM2DQSPADCTRL6 */ + uint32_t EmcXm2DqsPadCtrl6; + /* Specifies the value for EMC_XM2DQPADCTRL */ + uint32_t EmcXm2DqPadCtrl; + /* Specifies the value for EMC_XM2DQPADCTRL2 */ + uint32_t EmcXm2DqPadCtrl2; + /* Specifies the value for EMC_XM2DQPADCTRL3 */ + uint32_t EmcXm2DqPadCtrl3; + /* Specifies the value for EMC_XM2CLKPADCTRL */ + uint32_t EmcXm2ClkPadCtrl; + /* Specifies the value for EMC_XM2CLKPADCTRL2 */ + uint32_t EmcXm2ClkPadCtrl2; + /* Specifies the value for EMC_XM2COMPPADCTRL */ + uint32_t EmcXm2CompPadCtrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL */ + uint32_t EmcXm2VttGenPadCtrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL2 */ + uint32_t EmcXm2VttGenPadCtrl2; + /* Specifies the value for EMC_XM2VTTGENPADCTRL3 */ + uint32_t EmcXm2VttGenPadCtrl3; + /* Specifies the value for EMC_ACPD_CONTROL */ + uint32_t EmcAcpdControl; + + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ + uint32_t EmcSwizzleRank0ByteCfg; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ + uint32_t EmcSwizzleRank0Byte0; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ + uint32_t EmcSwizzleRank0Byte1; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ + uint32_t EmcSwizzleRank0Byte2; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ + uint32_t EmcSwizzleRank0Byte3; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ + uint32_t EmcSwizzleRank1ByteCfg; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ + uint32_t EmcSwizzleRank1Byte0; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ + uint32_t EmcSwizzleRank1Byte1; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ + uint32_t EmcSwizzleRank1Byte2; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ + uint32_t EmcSwizzleRank1Byte3; + + /* Specifies the value for EMC_DSR_VTTGEN_DRV */ + uint32_t EmcDsrVttgenDrv; + + /* Specifies the value for EMC_TXDSRVTTGEN */ + uint32_t EmcTxdsrvttgen; + /* Specifies the value for EMC_BGBIAS_CTL */ + uint32_t EmcBgbiasCtl0; + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + uint32_t McEmemAdrCfg; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + uint32_t McEmemAdrCfgDev0; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + uint32_t McEmemAdrCfgDev1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ + uint32_t McEmemAdrCfgBankMask0; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ + uint32_t McEmemAdrCfgBankMask1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ + uint32_t McEmemAdrCfgBankMask2; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG3 */ + uint32_t McEmemAdrCfgBankSwizzle3; + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + uint32_t McEmemCfg; + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + uint32_t McEmemArbCfg; + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + uint32_t McEmemArbOutstandingReq; + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + uint32_t McEmemArbTimingRcd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + uint32_t McEmemArbTimingRp; + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + uint32_t McEmemArbTimingRc; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + uint32_t McEmemArbTimingRas; + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + uint32_t McEmemArbTimingFaw; + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + uint32_t McEmemArbTimingRrd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + uint32_t McEmemArbTimingRap2Pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + uint32_t McEmemArbTimingWap2Pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + uint32_t McEmemArbTimingR2R; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + uint32_t McEmemArbTimingW2W; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + uint32_t McEmemArbTimingR2W; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + uint32_t McEmemArbTimingW2R; + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + uint32_t McEmemArbDaTurns; + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + uint32_t McEmemArbDaCovers; + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + uint32_t McEmemArbMisc0; + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + uint32_t McEmemArbMisc1; + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + uint32_t McEmemArbRing1Throttle; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + uint32_t McEmemArbOverride; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ + uint32_t McEmemArbOverride1; + /* Specifies the value for MC_EMEM_ARB_RSV */ + uint32_t McEmemArbRsv; + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + uint32_t McClkenOverride; + + /* Specifies the value for MC_STAT_CONTROL */ + uint32_t McStatControl; + /* Specifies the value for MC_DISPLAY_SNAP_RING */ + uint32_t McDisplaySnapRing; + /* Specifies the value for MC_VIDEO_PROTECT_BOM */ + uint32_t McVideoProtectBom; + /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ + uint32_t McVideoProtectBomAdrHi; + /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ + uint32_t McVideoProtectSizeMb; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ + uint32_t McVideoProtectVprOverride; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ + uint32_t McVideoProtectVprOverride1; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ + uint32_t McVideoProtectGpuOverride0; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ + uint32_t McVideoProtectGpuOverride1; + /* Specifies the value for MC_SEC_CARVEOUT_BOM */ + uint32_t McSecCarveoutBom; + /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ + uint32_t McSecCarveoutAdrHi; + /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ + uint32_t McSecCarveoutSizeMb; + /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL. + VIDEO_PROTECT_WRITE_ACCESS */ + uint32_t McVideoProtectWriteAccess; + /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL. + SEC_CARVEOUT_WRITE_ACCESS */ + uint32_t McSecCarveoutProtectWriteAccess; + + /* Specifies enable for CA training */ + uint32_t EmcCaTrainingEnable; + /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL1 */ + uint32_t EmcCaTrainingTimingCntl1; + /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL2 */ + uint32_t EmcCaTrainingTimingCntl2; + /* Set if bit 6 select is greater than bit 7 select; uses aremc. + spec packet SWIZZLE_BIT6_GT_BIT7 */ + uint32_t SwizzleRankByteEncode; + /* Specifies enable and offset for patched boot rom write */ + uint32_t BootRomPatchControl; + /* Specifies data for patched boot rom write */ + uint32_t BootRomPatchData; + /* Specifies the value for MC_MTS_CARVEOUT_BOM */ + uint32_t McMtsCarveoutBom; + /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ + uint32_t McMtsCarveoutAdrHi; + /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ + uint32_t McMtsCarveoutSizeMb; + /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ + uint32_t McMtsCarveoutRegCtrl; + + /* End of generated code by warmboot_code_gen */ +}; + +check_member(sdram_params, McMtsCarveoutRegCtrl, 0x4d0); + +#endif /* __SOC_NVIDIA_TEGRA132_SDRAM_PARAM_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/spi.h b/src/soc/nvidia/tegra132/include/soc/spi.h new file mode 100644 index 0000000000..2fd9562599 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/spi.h @@ -0,0 +1,72 @@ +/* + * Copyright 2014 Google Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __NVIDIA_TEGRA132_SPI_H__ +#define __NVIDIA_TEGRA132_SPI_H__ + +#include <soc/dma.h> +#include <spi-generic.h> +#include <stddef.h> + +struct tegra_spi_regs { + u32 command1; /* 0x000: SPI_COMMAND1 */ + u32 command2; /* 0x004: SPI_COMMAND2 */ + u32 timing1; /* 0x008: SPI_CS_TIM1 */ + u32 timing2; /* 0x00c: SPI_CS_TIM2 */ + u32 trans_status; /* 0x010: SPI_TRANS_STATUS */ + u32 fifo_status; /* 0x014: SPI_FIFO_STATUS */ + u32 tx_data; /* 0x018: SPI_TX_DATA */ + u32 rx_data; /* 0x01c: SPI_RX_DATA */ + u32 dma_ctl; /* 0x020: SPI_DMA_CTL */ + u32 dma_blk; /* 0x024: SPI_DMA_BLK */ + u32 rsvd[56]; /* 0x028-0x107: reserved */ + u32 tx_fifo; /* 0x108: SPI_FIFO1 */ + u32 rsvd2[31]; /* 0x10c-0x187 reserved */ + u32 rx_fifo; /* 0x188: SPI_FIFO2 */ + u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */ +} __attribute__((packed)); +check_member(tegra_spi_regs, spare_ctl, 0x18c); + +enum spi_xfer_mode { + XFER_MODE_NONE = 0, + XFER_MODE_PIO, + XFER_MODE_DMA, +}; + +struct tegra_spi_channel { + struct tegra_spi_regs *regs; + + /* static configuration */ + struct spi_slave slave; + unsigned int req_sel; + + int dual_mode; /* for x2 transfers with bit interleaving */ + + /* context (used internally) */ + u8 *in_buf, *out_buf; + struct apb_dma_channel *dma_out, *dma_in; + enum spi_xfer_mode xfer_mode; +}; + +struct cbfs_media; +int initialize_tegra_spi_cbfs_media(struct cbfs_media *media, + void *buffer_address, + size_t buffer_size); + +struct tegra_spi_channel *tegra_spi_init(unsigned int bus); + +#endif /* __NVIDIA_TEGRA132_SPI_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/sysctr.h b/src/soc/nvidia/tegra132/include/soc/sysctr.h new file mode 100644 index 0000000000..ea9746ddf2 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/sysctr.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_SYSCTR_H__ +#define __SOC_NVIDIA_TEGRA132_SYSCTR_H__ + +#include <stdint.h> + +enum { + SYSCTR_CNTCR_EN = 1 << 0, + SYSCTR_CNTCR_HDBG = 1 << 1, + SYSCTR_CNTCR_FCREQ = 1 << 8 +}; + +struct sysctr_regs { + uint32_t cntcr; + uint32_t cntsr; + uint32_t cntcv0; + uint32_t cntcv1; + uint8_t _rsv0[0x10]; + uint32_t cntfid0; + uint32_t cntfid1; + uint8_t _rsv1[0xfa8]; + uint32_t counterid4; + uint32_t counterid5; + uint32_t counterid6; + uint32_t counterid7; + uint32_t counterid0; + uint32_t counterid1; + uint32_t counterid2; + uint32_t counterid3; + uint32_t counterid8; + uint32_t counterid9; + uint32_t counterid10; + uint32_t counterid11; +}; +check_member(sysctr_regs, counterid11, 0xffc); + +#endif /* __SOC_NVIDIA_TEGRA132_SYSCTR_H__ */ |