t132: Implement clock initialization api for functional units

This api provides a common interface to initialize various clock sources,
dividers as well as enabling the clock for various functional units.

BUG=chrome-os-partner:31251
BRANCH=None
TEST=Compiles successfully for rush and boots till last known good point.

Change-Id: I2b8df5abf7301bc940315427af4cb38a635f07f8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9814f93a9f99fc9df6267167f991ebef427e9ae3
Original-Change-Id: I7abb193d6a9cfa448df1c48c346b4edbad802329
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211765
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8921
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2 files changed, 72 insertions, 3 deletions

diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h
index 5259c18011..6f98e3c618 100644
--- a/src/soc/nvidia/tegra132/include/soc/clock.h
+++ b/src/soc/nvidia/tegra132/include/soc/clock.h
@@ -236,9 +236,14 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
 			src << CLK_SOURCE_SHIFT | div);
 }
 
+#define get_i2c_clk_div(src,freq) (div_round_up(src, (freq) * (0x19 + 1) * 8) - 1)
+#define get_clk_div(src,freq)     CLK_DIVIDER(src,freq)
+#define CLK_DIV_MASK              0xff
+#define CLK_DIV_MASK_I2C          0xffff
+
 #define clock_configure_irregular_source(device, src, freq, src_id) \
 	_clock_set_div(&clk_rst->clk_src_##device, #device, \
-		CLK_DIVIDER(TEGRA_##src##_KHZ, freq), 0xff, src_id)
+		       get_clk_div(TEGRA_##src##_KHZ, freq), CLK_DIV_MASK, src_id)
 
 /* Warning: Some devices just use different bits for the same sources for no
  * apparent reason. *Always* double-check the TRM before trusting this macro. */
@@ -254,8 +259,8 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
  */
 #define clock_configure_i2c_scl_freq(device, src, freq) \
 	_clock_set_div(&clk_rst->clk_src_##device, #device, \
-		div_round_up(TEGRA_##src##_KHZ, (freq) * (0x19 + 1) * 8) - 1, \
-		0xffff, src)
+		       get_i2c_clk_div(TEGRA_##src##_KHZ, freq),	\
+		       CLK_DIV_MASK_I2C, src)
 
 enum clock_source {  /* Careful: Not true for all sources, always check TRM! */
 	PLLP = 0,
@@ -288,6 +293,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
 void clock_cpu0_config(void);
 void clock_halt_avp(void);
 void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
+void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32* rst_dev_clr_reg);
 void clock_reset_l(u32 l);
 void clock_reset_h(u32 h);
 void clock_reset_u(u32 u);
diff --git a/src/soc/nvidia/tegra132/include/soc/funitcfg.h b/src/soc/nvidia/tegra132/include/soc/funitcfg.h
new file mode 100644
index 0000000000..7612d76af3
--- /dev/null
+++ b/src/soc/nvidia/tegra132/include/soc/funitcfg.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H
+#define __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H
+
+#include <stdint.h>
+#include <soc/nvidia/tegra132/pinmux.h>
+#include <soc/padconfig.h>
+#include <soc/clock.h>
+
+#define FUNIT_INDEX(_name)  FUNIT_##_name
+
+enum {
+	FUNIT_NONE = 0,
+	FUNIT_INDEX(SBC1),
+	FUNIT_INDEX(SBC4),
+	FUNIT_INDEX(I2C3),
+	FUNIT_INDEX(I2C5),
+	FUNIT_INDEX(SDMMC3),
+	FUNIT_INDEX(SDMMC4),
+	FUNIT_INDEX_MAX,
+};
+
+struct funit_cfg {
+	uint32_t funit_index;
+	uint32_t clk_src_id;
+	uint32_t clk_dev_freq_khz;
+	struct pad_config const* pad_cfg;
+	size_t pad_cfg_size;
+};
+
+#define FUNIT_CFG(_funit,_clk_src,_clk_freq,_cfg,_cfg_size)		\
+	{								\
+		.funit_index = FUNIT_INDEX(_funit),			\
+		.clk_src_id = _clk_src,					\
+		.clk_dev_freq_khz = _clk_freq,				\
+		.pad_cfg = _cfg,					\
+		.pad_cfg_size = _cfg_size,				\
+	}
+
+/*
+ * Configure the funits associated with entry according to the configuration.
+ */
+void soc_configure_funits(const struct funit_cfg * const entries, size_t num);
+
+#endif /* __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H */