diff options
| author | Jimmy Zhang <jimmzhang@nvidia.com> | 2015-01-06 14:14:24 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-14 09:04:37 +0200 |
| commit | 51b314b5838063ac5fea6687ebade95039889f51 (patch) | |
| tree | 50d891043f27dcdeb8cb4df0f8a3c0f35629445a /src/soc/nvidia/tegra132/dsi.c | |
| parent | d046fe86d8388b1a792538dfc9eda627885cb12b (diff) | |
ryu: display: Set display shift clock divider
Add and call display shift clock divider function to set shift clock
divider.
This change is also intended for code sharing on dc settings.
BUG=chrome-os-partner:34336
BRANCH=none
TEST=build ryu and rush
Change-Id: I9ad1b32de50395720355bb2d00f5800c7f6c4b73
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24a72fa3411652d54ae1f7d69db0a7293aad7877
Original-Change-Id: I01582c6863d31627ac93db9fddda93f4f78249cd
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/238943
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9614
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132/dsi.c')
| -rw-r--r-- | src/soc/nvidia/tegra132/dsi.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra132/dsi.c b/src/soc/nvidia/tegra132/dsi.c index ad27b3d8b4..af2f592aa0 100644 --- a/src/soc/nvidia/tegra132/dsi.c +++ b/src/soc/nvidia/tegra132/dsi.c @@ -430,11 +430,14 @@ static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, static int tegra_output_dsi_setup_clock(struct tegra_dsi *dsi, const struct soc_nvidia_tegra132_config *config) { - unsigned int mul, div, num_lanes; // , vrefresh, num_lanes; + unsigned int mul, div, num_lanes; unsigned long bclk; unsigned long pclk = config->pixel_clock; int plld; int err; + struct display_controller *disp_ctrl = + (void *)config->display_controller; + unsigned int shift_clk_div; err = tegra_dsi_get_muldiv(dsi->format, &mul, &div); if (err < 0) @@ -471,6 +474,15 @@ static int tegra_output_dsi_setup_clock(struct tegra_dsi *dsi, return -1; } + /* + * Derive pixel clock from bit clock using the shift clock divider. + * Note that this is only half of what we would expect, but we need + * that to make up for the fact that we divided the bit clock by a + * factor of two above. + */ + shift_clk_div = ((8 * mul) / (div * num_lanes)) - 2; + update_display_shift_clock_divider(disp_ctrl, shift_clk_div); + tegra_dsi_set_timeout(dsi, bclk, config->refresh); return plld/1000000; } |