diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-11-19 11:57:47 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-10 20:44:41 +0200 |
| commit | 4b0853246f7ec9ae8e89e81c03da7e36c8ce8296 (patch) | |
| tree | 7b3eb5be124aea4a4d9c069639b55b89b0483782 /src/soc/nvidia/tegra132/display.c | |
| parent | bcea3f64a3fd12f8c068e55108ef3e9a9d46acae (diff) | |
tegra132: rename clock_display() to clock_configure_plld()
Provide an explicit name for configuring PLLD. The new name,
clock_configure_plld(), provides an explicit semantic to
what it is doing. Also, provide the printk() about actual
frequency vs requested frequency as most of the callers
were doing this themselves.
BUG=chrome-os-partner:33825
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: I1880f0f305e69674922b070d282aac3acdc86aad
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c51d5b0864d8bd0db5927380803cec46ccd74d48
Original-Change-Id: If744332b466d9486f83b08d0ab4e9006fadfecdd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230773
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: http://review.coreboot.org/9524
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132/display.c')
| -rw-r--r-- | src/soc/nvidia/tegra132/display.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/soc/nvidia/tegra132/display.c b/src/soc/nvidia/tegra132/display.c index 4fc312ebec..d616b7356f 100644 --- a/src/soc/nvidia/tegra132/display.c +++ b/src/soc/nvidia/tegra132/display.c @@ -135,7 +135,8 @@ static int update_display_mode(struct display_controller *disp_ctrl, * has some requirements to have VCO in range 500MHz~1000MHz (see * clock.c for more detail). To simplify calculation, we set * PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values - * may be calculated by clock_display, to allow wider frequency range. + * may be calculated by clock_configure_plld(), to allow wider + * frequency range. * * Note ShiftClockDiv is a 7.1 format value. */ @@ -265,12 +266,10 @@ void display_startup(device_t dev) * update_display_mode() for detail. */ /* set default plld */ - plld_rate = clock_display(config->pixel_clock * 2); + plld_rate = clock_configure_plld(config->pixel_clock * 2); if (plld_rate == 0) { printk(BIOS_ERR, "dc: clock init failed\n"); return; - } else if (plld_rate != config->pixel_clock * 2) { - printk(BIOS_WARNING, "dc: plld rounded to %u\n", plld_rate); } /* set disp1's clock source to PLLD_OUT0 */ |