diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-11-19 11:57:47 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-10 20:44:41 +0200 |
| commit | 4b0853246f7ec9ae8e89e81c03da7e36c8ce8296 (patch) | |
| tree | 7b3eb5be124aea4a4d9c069639b55b89b0483782 /src/soc/nvidia/tegra132/clock.c | |
| parent | bcea3f64a3fd12f8c068e55108ef3e9a9d46acae (diff) | |
tegra132: rename clock_display() to clock_configure_plld()
Provide an explicit name for configuring PLLD. The new name,
clock_configure_plld(), provides an explicit semantic to
what it is doing. Also, provide the printk() about actual
frequency vs requested frequency as most of the callers
were doing this themselves.
BUG=chrome-os-partner:33825
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: I1880f0f305e69674922b070d282aac3acdc86aad
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c51d5b0864d8bd0db5927380803cec46ccd74d48
Original-Change-Id: If744332b466d9486f83b08d0ab4e9006fadfecdd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230773
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: http://review.coreboot.org/9524
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132/clock.c')
| -rw-r--r-- | src/soc/nvidia/tegra132/clock.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index 49c2f19dac..661d38a55d 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -291,10 +291,6 @@ static void graphics_pll(void) /* leave dither and undoc bits set, release clamp */ scfg = (1<<28) | (1<<24); writel(scfg, cfg); - - /* disp1 will be set when panel information (pixel clock) is - * retrieved (clock_display). - */ } /* @@ -304,8 +300,7 @@ static void graphics_pll(void) * * Return the plld frequency if success, otherwise return 0. */ -u32 -clock_display(u32 frequency) +u32 clock_configure_plld(u32 frequency) { /** * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz @@ -388,6 +383,10 @@ clock_display(u32 frequency) init_pll(CLK_RST_REG(plld_base), CLK_RST_REG(plld_misc), plld, (PLLUD_MISC_LOCK_ENABLE | PLLD_MISC_CLK_ENABLE)); + if (rounded_rate != frequency) + printk(BIOS_DEBUG, "PLLD rate: %u vs %u\n", rounded_rate, + frequency); + return rounded_rate; } |