diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-09-20 15:07:52 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-28 08:44:55 +0100 |
| commit | 68a672c2c268295136e1ca186cab390494088490 (patch) | |
| tree | ba8afb65f303196b2cefc1640695c0feb371393c /src/soc/nvidia/tegra132/ccplex.c | |
| parent | cd72103021a318741cd6bb51efe585ef09f0ce2b (diff) | |
tegra132: Clean up clock register writes
Clean up functions to write to clk_enb and rst_dev registers and add
clock_disable and clock_set_reset functions to provide a complete API for
updating the registers.
BUG=chrome-os-partner:31821
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on ryu. Compiles
successfully on rush
Change-Id: Ib0b7e3fc322f18be396ecf3b02b2399d4ba33e9b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1bb222adc22c7e26077dfb2ba6e4d41a4965d183
Original-Change-Id: Icb8081fe3d80174c920eaaecf5cbb0aa912d5b19
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219191
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9099
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/nvidia/tegra132/ccplex.c')
| -rw-r--r-- | src/soc/nvidia/tegra132/ccplex.c | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c index 1085b285ad..258fbea3ab 100644 --- a/src/soc/nvidia/tegra132/ccplex.c +++ b/src/soc/nvidia/tegra132/ccplex.c @@ -23,6 +23,7 @@ #include <cbfs.h> #include <timer.h> #include <soc/addressmap.h> +#include <soc/clock.h> #include <soc/cpu.h> #include <soc/romstage.h> #include "clk_rst.h" @@ -109,16 +110,8 @@ int ccplex_load_mts(void) static void enable_cpu_clocks(void) { - struct clk_rst_ctlr * const clk_rst = CLK_RST_REGS; - uint32_t reg; - - reg = read32(&clk_rst->clk_enb_l_set); - reg |= CLK_ENB_CPU; - write32(reg, &clk_rst->clk_enb_l_set); - - reg = read32(&clk_rst->clk_enb_v_set); - reg |= SET_CLK_ENB_CPUG_ENABLE | SET_CLK_ENB_CPULP_ENABLE; - write32(reg, &clk_rst->clk_enb_v_set); + clock_enable(CLK_ENB_CPU, 0, 0, SET_CLK_ENB_CPUG_ENABLE | + SET_CLK_ENB_CPULP_ENABLE, 0, 0); } static void enable_cpu_power_partitions(void) |