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authorAaron Durbin <adurbin@chromium.org>2014-04-24 11:35:28 -0500
committerMarc Jones <marc.jones@se-eng.com>2014-12-17 20:50:58 +0100
commit59e209af890a7e58f4c74718a2dec567bbd0d58e (patch)
tree6be60c5ac320cc60e9871821d529300849202c23 /src/soc/nvidia/tegra124
parenta081305729938448dc66ed2e9b2c48ef89ea4356 (diff)
baytrail: initialize backlight PWM frequency
In order to protect ourselves from the kernel driver not honoring or placing the correct frequency in the backlight register always set one. This code path picks 200Hz as the default if nothing is specified in device tree. It's somewhat arbitrary but that frequency is valid for all the eDP panel specs we've seen being used on baytrail devices. BUG=chrome-os-partner:28267 BRANCH=baytrail TEST=Built and booted in normal mode. Noted register write stuck. Original-Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196821 Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com> (cherry picked from commit 2eaa650860ebbc838dbf8c1c1ca2259ac64141ac) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5 Reviewed-on: http://review.coreboot.org/7845 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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