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authorDaisuke Nojiri <dnojiri@chromium.org>2014-06-19 19:16:24 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-01-27 01:43:01 +0100
commitbcc1d422a2508dc54737fd941336c8cc09c51de1 (patch)
treec5912b1551b86641d4685be56f5e4578a086e281 /src/soc/nvidia/tegra124
parent77b1655d9bccd0c93cb1a6b86ecc98e2074504a3 (diff)
vboot2: implement select_firmware for pre-romstage verification
This patch has a basic structure of vboot2 integration. It supports only Nyans, which have bootblock architecture and romstage architecture are compatible from linker's perspective. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I4bbd4d0452604943b376bef20ea8a258820810aa Original-Reviewed-on: https://chromium-review.googlesource.com/204522 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit a6bce0cbed34def60386f3d9aece59e739740c58) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I63ddfbf463c8a83120828ec8ab994f8146f90001 Reviewed-on: http://review.coreboot.org/8160 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/nvidia/tegra124')
-rw-r--r--src/soc/nvidia/tegra124/Kconfig11
-rw-r--r--src/soc/nvidia/tegra124/Makefile.inc8
-rw-r--r--src/soc/nvidia/tegra124/verstage.c8
3 files changed, 26 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index f0cef82889..a8fcbfb3f6 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -46,10 +46,12 @@ config BOOTBLOCK_ROM_OFFSET
config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM"
+ default 0x1e000 if VBOOT2_VERIFY_FIRMWARE
default 0x18000
config CBFS_ROM_OFFSET
hex "offset of CBFS data in ROM"
+ default 0x1e080 if VBOOT2_VERIFY_FIRMWARE
default 0x18080
config SYS_SDRAM_BASE
@@ -62,6 +64,7 @@ config BOOTBLOCK_BASE
config ROMSTAGE_BASE
hex
+ default 0x4002d000 if VBOOT2_VERIFY_FIRMWARE
default 0x4002c000
config RAMSTAGE_BASE
@@ -94,6 +97,14 @@ config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
default 0x00017fe0
+config VBOOT_WORK_BUFFER_ADDRESS
+ hex "memory address of vboot work buffer"
+ default 0x40018000
+
+config VBOOT_WORK_BUFFER_SIZE
+ hex "size of vboot work buffer"
+ default 0x00004000
+
config TEGRA124_MODEL_TD570D
bool "TD570D"
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index b306412956..4b0ec9649f 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -21,6 +21,14 @@ bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c
endif
verstage-y += verstage.c
+verstage-y += cbfs.c
+verstage-y += dma.c
+verstage-y += monotonic_timer.c
+verstage-y += spi.c
+verstage-y += timer.c
+verstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
+verstage-y += ../tegra/gpio.c
+verstage-y += ../tegra/pinmux.c
romstage-y += cbfs.c
romstage-y += cbmem.c
diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c
index 234a89d0b2..d85fc5c8cf 100644
--- a/src/soc/nvidia/tegra124/verstage.c
+++ b/src/soc/nvidia/tegra124/verstage.c
@@ -1,9 +1,15 @@
#include "verstage.h"
+#include <vendorcode/google/chromeos/chromeos.h>
/**
* Stage entry point
*/
void vboot_main(void)
{
- for(;;);
+ /* Stub to force arm_init_caches to the top, before any stack/memory
+ * accesses */
+ asm volatile ("bl arm_init_caches"
+ ::: "r0","r1","r2","r3","r4","r5","ip");
+
+ select_firmware();
}