diff options
| author | Jimmy Zhang <jimmzhang@nvidia.com> | 2014-04-14 12:15:38 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-12-16 23:22:48 +0100 |
| commit | 84b8be6a97806bb4a98846ef449440f6950de727 (patch) | |
| tree | fc5de652948334d188d56ea38e96102ea372d2a2 /src/soc/nvidia/tegra124 | |
| parent | f682ad0ebba39454b408f1b022e152f4b59a5e79 (diff) | |
nyan*: merge a couple of sor setting difference from kernel driver
BRANCH=none
BUG=chrome-os-partner:27413
TEST=build nyan and nyan_big. nyan display works fine.
nyan_big display still does't work until all related
patches are built in. (CL:194739)
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: Ic5d977f695be127693f1ecc3ba52d478f524d20f
Original-Reviewed-on: https://chromium-review.googlesource.com/194737
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit ef3208d8ff3c3dcfaeda9c0146bf1ae920682dea)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ide1cd28ecc0ae1cd4d8603a52975592daee4bce8
Reviewed-on: http://review.coreboot.org/7766
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/nvidia/tegra124')
| -rw-r--r-- | src/soc/nvidia/tegra124/sor.c | 24 |
1 files changed, 18 insertions, 6 deletions
diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 5d463a8a81..4a5da38530 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -248,6 +248,23 @@ void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor, tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val); } +static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div, + u32 pwm_dutycycle) +{ + tegra_sor_writel(sor, NV_SOR_PWM_DIV, pwm_div); + tegra_sor_writel(sor, NV_SOR_PWM_CTL, + (pwm_dutycycle & NV_SOR_PWM_CTL_DUTY_CYCLE_MASK) | + NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER); + + if (tegra_dc_sor_poll_register(sor, NV_SOR_PWM_CTL, + NV_SOR_PWM_CTL_SETTING_NEW_SHIFT, + NV_SOR_PWM_CTL_SETTING_NEW_DONE, + 100, TEGRA_SOR_TIMEOUT_MS * 1000)) { + printk(BIOS_ERR, + "dp: timeout while waiting for SOR PWM setting\n"); + } +} + static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor, const struct tegra_dc_dp_link_config *link_cfg) { @@ -274,11 +291,6 @@ static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor, tegra_sor_writel(sor, NV_SOR_DP_CONFIG(sor->portnum), reg_val); - /* enable CRC */ - reg_val = NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_EN << - NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_SHIFT; - tegra_sor_writel(sor, NV_SOR_CRC_CNTRL, reg_val); - /* program h/vblank sym */ tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK, link_cfg->hblank_sym); @@ -558,6 +570,7 @@ static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor, 2 << NV_SOR_CSTM_ROTCLK_SHIFT | (is_lvds ? NV_SOR_CSTM_LVDS_EN_ENABLE : NV_SOR_CSTM_LVDS_EN_DISABLE)); + tegra_dc_sor_config_pwm(sor, 1024, 1024); } static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor) @@ -571,7 +584,6 @@ static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor) WRITEL(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt); /* Enable DC */ - WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd); WRITEL(reg_val, &disp_ctrl->cmd.state_access); } |