Change all clrsetbits_leXX() to clrsetbitsXX()

This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

6 files changed, 59 insertions, 59 deletions

diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index bb0343d432..46ac4aca5d 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -203,13 +203,13 @@ void sor_clock_stop(void)
 	 * FIXME: this has to be cleaned up a bit more.
 	 * Waiting on some new info from Nvidia.
 	 */
-	clrbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0 | SOR0_CLK_SEL1);
+	clrbits32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0 | SOR0_CLK_SEL1);
 }
 
 void sor_clock_start(void)
 {
 	/* uses PLLP, has a non-standard bit layout. */
-	setbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0);
+	setbits32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0);
 }
 
 static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock)
@@ -240,7 +240,7 @@ static void init_utmip_pll(void)
 	int khz = clock_get_pll_input_khz();
 
 	/* Shut off PLL crystal clock while we mess with it */
-	clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
+	clrbits32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
 	udelay(1);
 
 	write32(&clk_rst->utmip_pll_cfg0,	/* 960MHz * 1 / 80 == 12 MHz */
@@ -263,7 +263,7 @@ static void init_utmip_pll(void)
 				  0 <<  2 |	/* SAMP_B/XHOST pwrdn */
 				  0 <<  0);	/* SAMP_A/USBD pwrdn */
 
-	setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
+	setbits32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
 }
 
 /* Graphics just has to be different. There's a few more bits we
@@ -401,9 +401,9 @@ void clock_early_uart(void)
 {
 	write32(&clk_rst->clk_src_uarta, CLK_M << CLK_SOURCE_SHIFT |
 		CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900));
-	setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA);
+	setbits32(&clk_rst->clk_out_enb_l, CLK_L_UARTA);
 	udelay(2);
-	clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA);
+	clrbits32(&clk_rst->rst_dev_l, CLK_L_UARTA);
 }
 
 /* Enable output clock (CLK1~3) for external peripherals. */
@@ -411,13 +411,13 @@ void clock_external_output(int clk_id)
 {
 	switch (clk_id) {
 	case 1:
-		setbits_le32(&pmc->clk_out_cntrl, 1 << 2);
+		setbits32(&pmc->clk_out_cntrl, 1 << 2);
 		break;
 	case 2:
-		setbits_le32(&pmc->clk_out_cntrl, 1 << 10);
+		setbits32(&pmc->clk_out_cntrl, 1 << 10);
 		break;
 	case 3:
-		setbits_le32(&pmc->clk_out_cntrl, 1 << 18);
+		setbits32(&pmc->clk_out_cntrl, 1 << 18);
 		break;
 	default:
 		printk(BIOS_CRIT, "ERROR: Unknown output clock id %d\n",
@@ -461,7 +461,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
 		 (p << PLL_BASE_DIVP_SHIFT));
 	write32(&clk_rst->pllm_base, base);
 
-	setbits_le32(&clk_rst->pllm_base, PLL_BASE_ENABLE);
+	setbits32(&clk_rst->pllm_base, PLL_BASE_ENABLE);
 	/* stable_time is required, before we can start to check lock. */
 	udelay(stable_time);
 
@@ -475,7 +475,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
 	udelay(10);
 
 	/* Put OUT1 out of reset state (start to output). */
-	setbits_le32(&clk_rst->pllm_out, PLLM_OUT1_RSTN_RESET_DISABLE);
+	setbits32(&clk_rst->pllm_out, PLLM_OUT1_RSTN_RESET_DISABLE);
 
 	/* Enable and start MEM(MC) and EMC. */
 	clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0);
@@ -492,7 +492,7 @@ void clock_cpu0_config(void *entry)
 	write32(evp_cpu_reset, (uintptr_t)&maincpu_setup);
 
 	/* Set active CPU cluster to G */
-	clrbits_le32(&flow->cluster_control, 1);
+	clrbits32(&flow->cluster_control, 1);
 
 	// Set up cclk_brst and divider.
 	write32(&clk_rst->cclk_brst_pol,
@@ -511,9 +511,9 @@ void clock_cpu0_config(void *entry)
 	write32(&clk_rst->clk_cpu_cmplx_clr, cpu_cmplx_clr);
 
 	// Enable other CPU related clocks.
-	setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU);
-	setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG);
-	setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP);
+	setbits32(&clk_rst->clk_out_enb_l, CLK_L_CPU);
+	setbits32(&clk_rst->clk_out_enb_v, CLK_V_CPUG);
+	setbits32(&clk_rst->clk_out_enb_v, CLK_V_CPULP);
 }
 
 void clock_cpu0_remove_reset(void)
@@ -573,7 +573,7 @@ void clock_init(void)
 		SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT);
 
 	/* Change the oscillator drive strength (from U-Boot -- why?) */
-	clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK,
+	clrsetbits32(&clk_rst->osc_ctrl, OSC_XOFS_MASK,
 			OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
 
 	/*
@@ -581,11 +581,11 @@ void clock_init(void)
 	 * "should update same value in PMC_OSC_EDPD_OVER XOFS
 	 * field for warmboot "
 	 */
-	clrsetbits_le32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK,
+	clrsetbits32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK,
 			OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT);
 
 	/* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */
-	clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK);
+	clrbits32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK);
 
 	/* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
 	write32(&clk_rst->pllp_outa,
diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c
index 761bb6bce5..78a8d10e00 100644
--- a/src/soc/nvidia/tegra124/dma.c
+++ b/src/soc/nvidia/tegra124/dma.c
@@ -82,7 +82,7 @@ struct apb_dma_channel * const dma_claim(void)
 	 * Set global enable bit, otherwise register access to channel
 	 * DMA registers will not be possible.
 	 */
-	setbits_le32(&apb_dma->command, APB_COMMAND_GEN);
+	setbits32(&apb_dma->command, APB_COMMAND_GEN);
 
 	for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) {
 		regs = apb_dma_channels[i].regs;
@@ -122,7 +122,7 @@ void dma_release(struct apb_dma_channel * const channel)
 			return;
 	}
 
-	clrbits_le32(&apb_dma->command, APB_COMMAND_GEN);
+	clrbits32(&apb_dma->command, APB_COMMAND_GEN);
 }
 
 int dma_start(struct apb_dma_channel * const channel)
@@ -130,7 +130,7 @@ int dma_start(struct apb_dma_channel * const channel)
 	struct apb_dma_channel_regs *regs = channel->regs;
 
 	/* Set ENB bit for this channel */
-	setbits_le32(&regs->csr, APB_CSR_ENB);
+	setbits32(&regs->csr, APB_CSR_ENB);
 
 	return 0;
 }
@@ -140,7 +140,7 @@ int dma_stop(struct apb_dma_channel * const channel)
 	struct apb_dma_channel_regs *regs = channel->regs;
 
 	/* Clear ENB bit for this channel */
-	clrbits_le32(&regs->csr, APB_CSR_ENB);
+	clrbits32(&regs->csr, APB_CSR_ENB);
 
 	return 0;
 }
diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h
index 00744ce596..f99e786180 100644
--- a/src/soc/nvidia/tegra124/include/soc/clock.h
+++ b/src/soc/nvidia/tegra124/include/soc/clock.h
@@ -231,8 +231,8 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
 		printk(BIOS_ERR, "%s clock divisor overflow!", name);
 		hlt();
 	}
-	clrsetbits_le32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
-			src << CLK_SOURCE_SHIFT | div);
+	clrsetbits32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
+		     src << CLK_SOURCE_SHIFT | div);
 }
 
 #define clock_configure_irregular_source(device, src, freq, src_id) \
diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c
index 9f3e355ca4..3f1ee7ee95 100644
--- a/src/soc/nvidia/tegra124/power.c
+++ b/src/soc/nvidia/tegra124/power.c
@@ -93,12 +93,12 @@ int power_reset_status(void)
 void ram_repair(void)
 {
 	// Request RAM repair for cluster 0
-	setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
+	setbits32(&flow->ram_repair, RAM_REPAIR_REQ);
 	// Poll for completion
 	while (!(read32(&flow->ram_repair) & RAM_REPAIR_STS))
 		;
 	// Request RAM repair for cluster 1
-	setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
+	setbits32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
 	// Poll for completion
 	while (!(read32(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
 		;
diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c
index 9af116c56b..cf529257a7 100644
--- a/src/soc/nvidia/tegra124/sdram.c
+++ b/src/soc/nvidia/tegra124/sdram.c
@@ -34,7 +34,7 @@ static void sdram_patch(uintptr_t addr, uint32_t value)
 
 static void writebits(uint32_t value, uint32_t *addr, uint32_t mask)
 {
-	clrsetbits_le32(addr, mask, (value & mask));
+	clrsetbits32(addr, mask, (value & mask));
 }
 
 /* PMC must be configured before clock-enable and de-reset of MC/EMC. */
@@ -77,17 +77,17 @@ static void sdram_start_clocks(const struct sdram_params *param)
 static void sdram_deassert_clock_enable_signal(const struct sdram_params *param,
 					       struct tegra_pmc_regs *regs)
 {
-	clrbits_le32(&regs->por_dpd_ctrl,
-		     PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK);
+	clrbits32(&regs->por_dpd_ctrl,
+		  PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK);
 	udelay(param->PmcPorDpdCtrlWait);
 }
 
 static void sdram_deassert_sel_dpd(const struct sdram_params *param,
 				   struct tegra_pmc_regs *regs)
 {
-	clrbits_le32(&regs->por_dpd_ctrl,
-		     (PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK |
-		      PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK));
+	clrbits32(&regs->por_dpd_ctrl,
+		  (PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK |
+		   PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK));
 	/*
 	 * Note NVIDIA recommended to always do 10us delay here and ignore
 	 * BCT.PmcPorDpdCtrlWait.
@@ -439,8 +439,8 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param,
 					  struct tegra_emc_regs *regs)
 {
 	volatile uint32_t dummy = 0;
-	clrbits_le32(&regs->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK |
-				  EMC_PIN_CKE_MASK));
+	clrbits32(&regs->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK |
+			       EMC_PIN_CKE_MASK));
 	/*
 	 * Assert dummy read of PIN register to ensure above write to PIN
 	 * register went through. 200 is the recommended value by NVIDIA.
@@ -449,7 +449,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param,
 	udelay(200 + param->EmcPinExtraWait);
 
 	/* Deassert reset */
-	setbits_le32(&regs->pin, EMC_PIN_RESET_INACTIVE);
+	setbits32(&regs->pin, EMC_PIN_RESET_INACTIVE);
 	/*
 	 * Assert dummy read of PIN register to ensure above write to PIN
 	 * register went through. 200 is the recommended value by NVIDIA.
@@ -458,7 +458,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param,
 	udelay(500 + param->EmcPinExtraWait);
 
 	/* Enable clock enable signal */
-	setbits_le32(&regs->pin, EMC_PIN_CKE_NORMAL);
+	setbits32(&regs->pin, EMC_PIN_CKE_NORMAL);
 	/*
 	 * Assert dummy read of PIN register to ensure above write to PIN
 	 * register went through. 200 is the recommended value by NVIDIA.
@@ -547,8 +547,8 @@ static void sdram_enable_arbiter(const struct sdram_params *param)
 {
 	/* TODO(hungte) Move values here to standalone header file. */
 	uint32_t *AHB_ARBITRATION_XBAR_CTRL = (uint32_t*)(0x6000c000 + 0xe0);
-	setbits_le32(AHB_ARBITRATION_XBAR_CTRL,
-		     param->AhbArbitrationXbarCtrlMemInitDone << 16);
+	setbits32(AHB_ARBITRATION_XBAR_CTRL,
+		  param->AhbArbitrationXbarCtrlMemInitDone << 16);
 }
 
 static void sdram_lock_carveouts(const struct sdram_params *param,
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c
index 27ae1faf22..007d189bc9 100644
--- a/src/soc/nvidia/tegra124/spi.c
+++ b/src/soc/nvidia/tegra124/spi.c
@@ -184,13 +184,13 @@ struct tegra_spi_channel *tegra_spi_init(unsigned int bus)
 		return NULL;
 
 	/* software drives chip-select, set value to high */
-	setbits_le32(&spi->regs->command1,
+	setbits32(&spi->regs->command1,
 			SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL);
 
 	/* 8-bit transfers, unpacked mode, most significant bit first */
-	clrbits_le32(&spi->regs->command1,
+	clrbits32(&spi->regs->command1,
 			SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED);
-	setbits_le32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT);
+	setbits32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT);
 
 	return spi;
 }
@@ -265,7 +265,7 @@ static void dump_fifo_status(struct tegra_spi_channel *spi)
 
 static void clear_fifo_status(struct tegra_spi_channel *spi)
 {
-	clrbits_le32(&spi->regs->fifo_status,
+	clrbits32(&spi->regs->fifo_status,
 				SPI_FIFO_STATUS_ERR |
 				SPI_FIFO_STATUS_TX_FIFO_OVF |
 				SPI_FIFO_STATUS_TX_FIFO_UNR |
@@ -372,11 +372,11 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi,
 		enable_mask = SPI_CMD1_RX_EN;
 	}
 
-	setbits_le32(&spi->regs->fifo_status, flush_mask);
+	setbits32(&spi->regs->fifo_status, flush_mask);
 	while (read32(&spi->regs->fifo_status) & flush_mask)
 		;
 
-	setbits_le32(&spi->regs->command1, enable_mask);
+	setbits32(&spi->regs->command1, enable_mask);
 
 	/* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and
 	 * PIO transfers */
@@ -396,8 +396,8 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi,
 
 static void tegra_spi_pio_start(struct tegra_spi_channel *spi)
 {
-	setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
-	setbits_le32(&spi->regs->command1, SPI_CMD1_GO);
+	setbits32(&spi->regs->trans_status, SPI_STATUS_RDY);
+	setbits32(&spi->regs->command1, SPI_CMD1_GO);
 	/* Make sure the write to command1 completes. */
 	read32(&spi->regs->command1);
 }
@@ -414,7 +414,7 @@ static int tegra_spi_pio_finish(struct tegra_spi_channel *spi)
 	u8 *p = spi->in_buf;
 	struct stopwatch sw;
 
-	clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN);
+	clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN);
 
 	/*
 	 * Allow some time in case the Rx FIFO does not yet have
@@ -446,19 +446,19 @@ static void setup_dma_params(struct tegra_spi_channel *spi,
 				struct apb_dma_channel *dma)
 {
 	/* APB bus width = 8-bits, address wrap for each word */
-	clrbits_le32(&dma->regs->apb_seq,
+	clrbits32(&dma->regs->apb_seq,
 			APB_BUS_WIDTH_MASK << APB_BUS_WIDTH_SHIFT);
 	/* AHB 1 word burst, bus width = 32 bits (fixed in hardware),
 	 * no address wrapping */
-	clrsetbits_le32(&dma->regs->ahb_seq,
+	clrsetbits32(&dma->regs->ahb_seq,
 			(AHB_BURST_MASK << AHB_BURST_SHIFT),
 			4 << AHB_BURST_SHIFT);
 
 	/* Set ONCE mode to transfer one "block" at a time (64KB) and enable
 	 * flow control. */
-	clrbits_le32(&dma->regs->csr,
+	clrbits32(&dma->regs->csr,
 			APB_CSR_REQ_SEL_MASK << APB_CSR_REQ_SEL_SHIFT);
-	setbits_le32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW |
+	setbits32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW |
 			(spi->req_sel << APB_CSR_REQ_SEL_SHIFT));
 }
 
@@ -493,7 +493,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
 		write32(&spi->dma_out->regs->apb_ptr,
 			(u32)&spi->regs->tx_fifo);
 		write32(&spi->dma_out->regs->ahb_ptr, (u32)spi->out_buf);
-		setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR);
+		setbits32(&spi->dma_out->regs->csr, APB_CSR_DIR);
 		setup_dma_params(spi, spi->dma_out);
 		write32(&spi->dma_out->regs->wcount, wcount);
 	} else {
@@ -506,7 +506,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
 
 		write32(&spi->dma_in->regs->apb_ptr, (u32)&spi->regs->rx_fifo);
 		write32(&spi->dma_in->regs->ahb_ptr, (u32)spi->in_buf);
-		clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR);
+		clrbits32(&spi->dma_in->regs->csr, APB_CSR_DIR);
 		setup_dma_params(spi, spi->dma_in);
 		write32(&spi->dma_in->regs->wcount, wcount);
 	}
@@ -523,12 +523,12 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi)
 	 * (set bit to clear) between each transaction. Otherwise the next
 	 * transaction does not start.
 	 */
-	setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
+	setbits32(&spi->regs->trans_status, SPI_STATUS_RDY);
 
 	if (spi->dma_out)
-		setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
+		setbits32(&spi->regs->command1, SPI_CMD1_TX_EN);
 	if (spi->dma_in)
-		setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
+		setbits32(&spi->regs->command1, SPI_CMD1_RX_EN);
 
 	/*
 	 * To avoid underrun conditions, enable APB DMA before SPI DMA for
@@ -536,7 +536,7 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi)
 	 */
 	if (spi->dma_out)
 		dma_start(spi->dma_out);
-	setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
+	setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
 	if (spi->dma_in)
 		dma_start(spi->dma_in);
 
@@ -555,7 +555,7 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi)
 				dma_busy(spi->dma_in))
 			;	/* this shouldn't take long, no udelay */
 		dma_stop(spi->dma_in);
-		clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
+		clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN);
 		dma_release(spi->dma_in);
 	}
 
@@ -566,7 +566,7 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi)
 				dma_busy(spi->dma_out)) {
 			spi_delay(spi, todo - spi_byte_count(spi));
 		}
-		clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
+		clrbits32(&spi->regs->command1, SPI_CMD1_TX_EN);
 		dma_stop(spi->dma_out);
 		dma_release(spi->dma_out);
 	}