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| author | Philipp Hug <philipp@hug.cx> | 2018-09-08 19:48:19 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2018-09-13 15:33:46 +0000 |
| commit | 18764a328da0cf39ad83a658f9b84b99f220a30c (patch) | |
| tree | a16fde14c64ad333ce9f21aa2fd2902c6cd01d1c /src/soc/nvidia/tegra124 | |
| parent | 7524400242be26610df143b5d1d781f875239c45 (diff) | |
soc/sifive/fu540: Update clock settings according SiFive bootloader
The documentation unfortunately doesn't match what SiFive uses in their FSBL.
Use the same values as in FSBL to make DDR RAM work.
Change-Id: I844cc41ed197333adeae495e71ea70b4a9603650
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28582
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra124')
0 files changed, 0 insertions, 0 deletions