diff options
author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-20 08:47:58 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2019-08-09 20:46:41 +0000 |
commit | e2c24f783d78c582fb56625768b9ac424b5943c9 (patch) | |
tree | c04ace65174be7ede94de015e7115aa7053fdb5d /src/soc/nvidia/tegra124/spi.c | |
parent | 34c30565b0ef3b1ff79943768ecc2f4012bf6b86 (diff) |
soc/amd/picasso: Update i2c support
Change the stoneyridge definitions into picasso. The named 0 and 1
buses are controlled by the PSP and not directly accessible by host
firmware. I2C4 operates only in slave mode so is not added to to
the bus clear-after-reset sequence.
The I2C controller is fundamentally the same as on Stoney Ridge so
the ability to clear a potentially jammed bus is still required.
Program Picasso's new pad control registers in the MISC AcpiMmio
space according to the recommended settings.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ibbc5504ebc36654e28c79fe3ae17cc0d9255118f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/nvidia/tegra124/spi.c')
0 files changed, 0 insertions, 0 deletions