diff options
| author | Neil Chen <neilc@nvidia.com> | 2014-09-24 10:41:08 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2015-04-04 04:04:01 +0200 |
| commit | ac4fef83454243d75571bac627a8ec15d3fcd405 (patch) | |
| tree | 8915fc1166eb29fdf6f7f210f5e8df96c106eab5 /src/soc/nvidia/tegra124/sor.h | |
| parent | 8c440a6befb735a4c1c553f5ff2e4539ec50e490 (diff) | |
tegra124: use known-good drive for fast-train only
A higher drive setting is used for fast link training, once the
link training succeeds, a known-good drive setting will be used
for the main stream transactions.
For full link training sequence, the sink devices may ask for a
preferred drive setting, thus this drive setting should be used
for the main stream transactions too.
BUG=chrome-os-partner:32129
TEST=all panels on blaze/big devices work fine.
Original-Change-Id: Icc540650dc1329af07fd9ee4661eb7fad435fde4
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219544
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 13d6accfdbe678e785851057f0800a3bbef11bea)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: If2fe7d5621f15aa3134d2a3920220e149bb64be6
Reviewed-on: http://review.coreboot.org/9248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/nvidia/tegra124/sor.h')
| -rw-r--r-- | src/soc/nvidia/tegra124/sor.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra124/sor.h b/src/soc/nvidia/tegra124/sor.h index 4e4211e45e..569cdb970b 100644 --- a/src/soc/nvidia/tegra124/sor.h +++ b/src/soc/nvidia/tegra124/sor.h @@ -920,6 +920,7 @@ void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor); void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, const struct tegra_dc_dp_link_config *link_cfg); void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor); +void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor); void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor); void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor); void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, |