diff options
| author | Neil Chen <neilc@nvidia.com> | 2014-09-23 17:41:59 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2015-04-04 04:03:48 +0200 |
| commit | 8c440a6befb735a4c1c553f5ff2e4539ec50e490 (patch) | |
| tree | b881c957f768542ad740fc4a0ebbc8b06282c1f9 /src/soc/nvidia/tegra124/sor.h | |
| parent | 9dceb0e30abe5d91bca0c7d6af3fe82281e82865 (diff) | |
tegra124: add support for full DP link training
The original dp driver supports only fast link training and a
special drive setting is used for the link training sequence.
This might not be accepted by all panels. The better way is to
go through full link training sequence to negotiate for a best
drive setting.
With the change, dp driver will try fast link training first,
this is same as before. If it fails in fast link training, will
try full link training.
BUG=chrome-os-partner:32129
TEST=all panels on blaze/big devices work fine.
Original-Change-Id: I6f3402c4c5993a156c965c7f52b011d336a2946f
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219543
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 24966517d41252384af3c2784def36aebad42434)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I3e7e7e749e5c8a9f07ac6132859fcad6fc96c39c
Reviewed-on: http://review.coreboot.org/9247
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/soc/nvidia/tegra124/sor.h')
| -rw-r--r-- | src/soc/nvidia/tegra124/sor.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra124/sor.h b/src/soc/nvidia/tegra124/sor.h index bf6286871e..4e4211e45e 100644 --- a/src/soc/nvidia/tegra124/sor.h +++ b/src/soc/nvidia/tegra124/sor.h @@ -695,6 +695,7 @@ #define NV_SOR_DP_PADCTL_TX_PU_SHIFT (22) #define NV_SOR_DP_PADCTL_TX_PU_DISABLE (0 << 22) #define NV_SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22) +#define NV_SOR_DP_PADCTL_TX_PU_MASK (1 << 22) #define NV_SOR_DP_PADCTL_REG_CTRL_SHIFT (20) #define NV_SOR_DP_PADCTL_REG_CTRL_DEFAULT_MASK (0x3 << 20) #define NV_SOR_DP_PADCTL_VCMMODE_SHIFT (16) @@ -878,6 +879,8 @@ struct tegra_dc_dp_link_config { u32 drive_current; u32 preemphasis; u32 postcursor; + u8 aux_rd_interval; + u8 tps3_supported; }; /* TODO: just pull these up into one struct? Need to see how this impacts @@ -917,4 +920,8 @@ void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor); void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, const struct tegra_dc_dp_link_config *link_cfg); void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor); +void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor); +void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor); +void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, + u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported); #endif /*__TEGRA124_SOR_H__ */ |