diff options
| author | Julius Werner <jwerner@chromium.org> | 2015-02-19 20:19:23 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:22:40 +0200 |
| commit | 941847652406982f3c9944fdd98cce4029b533fb (patch) | |
| tree | af52ebeaa0245c9a3aa1e25c77f2271b67bff4a8 /src/soc/nvidia/tegra124/lp0 | |
| parent | 2f37bd65518865688b9234afce0d467508d6f465 (diff) | |
arm(64): Manually clean up the mess left by write32() transition
This patch is a manual cleanup of all the rubble left by coccinelle
waltzing through our code base. It's generally not very good with line
breaks and sometimes even eats comments, so this patch is my best
attempt at putting it all back together.
Also finally remove those hated writel()-style macros from the headers.
BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)
Change-Id: Id572f69c420c35577701feb154faa5aaf79cd13e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 817402a80ab77083728b55aed74b3b4202ba7f1d
Original-Change-Id: I3b0dcd6fe09fc4e3b83ee491625d6dced98e3047
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254865
Reviewed-on: http://review.coreboot.org/9837
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra124/lp0')
| -rw-r--r-- | src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 2ed2103d15..e8cd5716f4 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -275,7 +275,7 @@ inline static uint32_t read32(const void *addr) return *(volatile uint32_t *)addr; } -inline static void write32(uint32_t val, void *addr) +inline static void write32(void *addr, uint32_t val) { *(volatile uint32_t *)addr = val; } @@ -483,7 +483,10 @@ static void clear_cpu_resets(void) // Clear software controlled reset of the fast cluster. write32(clk_rst_rst_cpug_cmplx_clr_ptr, - CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3); + CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | + CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | + CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | + CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3); } @@ -513,8 +516,7 @@ static void power_on_partition(unsigned id) uint32_t bit = 0x1 << id; if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { // Partition is not on. Turn it on. - write32(pmc_ctlr_pwrgate_toggle_ptr, - id | PWRGATE_TOGGLE_START); + write32(pmc_ctlr_pwrgate_toggle_ptr, id | PWRGATE_TOGGLE_START); // Wait until the partition is powerd on. while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) |