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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2022-11-08 14:03:00 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-24 06:00:38 +0000 |
| commit | 969531b6d8c015c329f96840a1337d6b7e9c5595 (patch) | |
| tree | 0f1e5dccc203602c7fa182b4a9165cf02cb3cf62 /src/soc/nvidia/tegra124/lp0 | |
| parent | 1a97c89d7b22a92992131032b0cd587de9f33d64 (diff) | |
mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver
This mainboard has three Marvel PHYs connected to the internal SOC GbE
controllers. The default LED status after HW reset of this PHYs shows a
different mode than what is needed. LED[2] is not connected on this
mainboard.
This patch sets the following LED status:
LED[0] - 7 = On - 1000 Mbps Link, Off - Else
LED[1] - 1 = On - Link, Blink - Activity, Off - No Link
LED[2] - not connected
TEST=Try different register values to verify LED feature.
Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69387
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra124/lp0')
0 files changed, 0 insertions, 0 deletions