summaryrefslogtreecommitdiff
path: root/src/soc/nvidia/tegra124/lp0
diff options
context:
space:
mode:
authorMichael Niewöhner <foss@mniewoehner.de>2021-01-24 12:56:12 +0100
committerNico Huber <nico.h@gmx.de>2021-01-31 19:27:55 +0000
commit33c0aac3b642b1f2a3cef5d3c32b150148eee90a (patch)
tree15ea089b6030450ceea17b92b4092f0e0eb472e9 /src/soc/nvidia/tegra124/lp0
parentd8ab828e5b80448e4f44b3b739995fec79e750f6 (diff)
soc/intel/*: drop incomplete and unneeded check for DMI SRLOCK
Before enabling IO decode ranges, current code checks if the DMI SRLOCK is set to prevent inconsistencies between LPC PCI cfg registers and LPC DMI registers, when the latter are locked. DMI SRLOCK only applies to PCHs with on-package DMI, but not to PCH-H, PCH-S and others with discrete PCH packages. So this check is at least incomplete. Further, the lock gets applied by FSP and gets reset on a warm reset. Thus, there is no case where the lock would be already set at the places where the DMI registers get written currently. Drop the checks for the reasons mentioned above. Change-Id: I59554ce96bce7f7d1a4ba9b098be9e8466c68eac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49885 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra124/lp0')
0 files changed, 0 insertions, 0 deletions