tegra124/nyan: memory and display updates

tegra124: use pll_c_out1 as sclk parent
Reviewed-on: https://chromium-review.googlesource.com/180865
(cherry picked from commit 418337a5bde70df6a770222201c51bf3e8892d5f)

tegra124: take LP cluster out of reset
Reviewed-on: https://chromium-review.googlesource.com/180866
(cherry picked from commit 74cdc68ea9b29da9af313635787e82bacb9e23e3)

tegra124: norrin: display code clean up
Reviewed-on: https://chromium-review.googlesource.com/181003
(cherry picked from commit 63843ec61b3b47ffc985edcb589771591c5c9f17)

tegra124: Change the display hack to use window A
Reviewed-on: https://chromium-review.googlesource.com/182001
(cherry picked from commit ef245e42eb17b2eb0e8712f252353a95ee6fc01a)

tegra124: norrin: Initialize frame buffer
Reviewed-on: https://chromium-review.googlesource.com/182090
(cherry picked from commit b7c1d1b3c9519cbbe1615737aed4c4c0efed2167)

nyan: do not enable pull-ups on SPI1 (EC) data pins
Reviewed-on: https://chromium-review.googlesource.com/181063
(cherry picked from commit 2f55188501ebcae9e01b12831f152d4520c7047c)

tegra124: Add source for the LP0 resume blob.
Reviewed-on: https://chromium-review.googlesource.com/183152
(cherry picked from commit a00d099bf710c297320d7edff7f7c608283d1b0b)

tegra124: Revise Memory Controller registers structure definition.
Reviewed-on: https://chromium-review.googlesource.com/182992
(cherry picked from commit ae83564cdd1d46c8166df1a95703e8cb1060c0a1)

tegra124: Add more PMC register details.
Reviewed-on: https://chromium-review.googlesource.com/183231
(cherry picked from commit d62ed2c19693284f10c2a12f4295091de3ace829)

tegra124: Add SDRAM configuration header file from cbootimage.
Reviewed-on: https://chromium-review.googlesource.com/182613
(cherry picked from commit 193ed2a104af38f6c41a332a649ce06a3238e0a4)

tegra124: Revise sdram_param.h for Coreboot.
Reviewed-on: https://chromium-review.googlesource.com/182614
(cherry picked from commit 311b0568c5de627435a5b035a7a1e40ecc2672f8)

tegra124: Fix EMC base address.
Reviewed-on: https://chromium-review.googlesource.com/183602
(cherry picked from commit 587c8969292ccecfa29c7720bcf24c704ed4ac4e)

tegra124: Add EMC registers definition.
Reviewed-on: https://chromium-review.googlesource.com/183622
(cherry picked from commit 67a8e5c7e87a1cc6bf006ad806751b549ffd3d5a)

tegra124: Never touch MEM(MC)/EMC clocks in ramstage.
Reviewed-on: https://chromium-review.googlesource.com/183623
(cherry picked from commit 8e3bb34d4ae37feae89b4a39850b2988a334d023)

tegra124: use RAM_CODE[3:2] for ram code
Reviewed-on: https://chromium-review.googlesource.com/183833
(cherry picked from commit 0154239467064ffcbdb82fc4c6b629f5d0c3568d)

tegra124: Allow setting PLLM (clock for SDRAM).
Reviewed-on: https://chromium-review.googlesource.com/183621
(cherry picked from commit a534e5b7c61d655eedd409dbd7780a4f90d40683)

tegra124: SDRAM Initialization.
Reviewed-on: https://chromium-review.googlesource.com/182615
(cherry picked from commit 5a60ae93b0603ee0d4806132be0360f3b1612bce)

tegra124: Get RAM_CODE for SDRAM initialization.
Reviewed-on: https://chromium-review.googlesource.com/183781
(cherry picked from commit a5b7ce70525d7ffef3fac90b8eb14b3f3787f4d8)

Squashed 18 nyan/tegra commits for memory and display.

Change-Id: I59a781ee8dc2fd9c9085373f5a9bb7c8108b094c
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6914
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

3 files changed, 19 insertions, 3 deletions

diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h
index b3c0b2961d..5e55ee57e0 100644
--- a/src/soc/nvidia/tegra124/include/soc/addressmap.h
+++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h
@@ -66,9 +66,9 @@ enum {
 	TEGRA_SPI6_BASE =		TEGRA_APB_MISC_BASE + 0xDE00,
 	TEGRA_DVC_BASE =		TEGRA_APB_MISC_BASE + 0xD000,
 	TEGRA_PMC_BASE =		TEGRA_APB_MISC_BASE + 0xE400,
-	TEGRA_EMC_BASE =		TEGRA_APB_MISC_BASE + 0xF400,
 	TEGRA_FUSE_BASE =		TEGRA_APB_MISC_BASE + 0xF800,
 	TEGRA_MC_BASE =			0x70019000,
+	TEGRA_EMC_BASE =		0x7001B000,
 	TEGRA_CSITE_BASE =		0x70040000,
 	TEGRA_SYSCTR0_BASE =		0x700F0000,
 	TEGRA_USBD_BASE =		0x7D000000,
diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h
index 3ec36080c7..89be88b020 100644
--- a/src/soc/nvidia/tegra124/include/soc/clock.h
+++ b/src/soc/nvidia/tegra124/include/soc/clock.h
@@ -247,6 +247,9 @@ enum clock_source {  /* Careful: Not true for all sources, always check TRM! */
 int clock_get_osc_khz(void);
 void clock_early_uart(void);
 void clock_external_output(int clk_id);
+void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
+		 u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source,
+		 u32 same_freq);
 void clock_cpu0_config_and_reset(void * entry);
 void clock_halt_avp(void);
 void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
diff --git a/src/soc/nvidia/tegra124/include/soc/display.h b/src/soc/nvidia/tegra124/include/soc/display.h
index 27935d9cea..b764671134 100644
--- a/src/soc/nvidia/tegra124/include/soc/display.h
+++ b/src/soc/nvidia/tegra124/include/soc/display.h
@@ -44,6 +44,9 @@
 
 /* ardisplay_a.h */
 #define DC_WIN_A_WIN_OPTIONS_0			0x700
+#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT	30
+#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_FIELD	(0x1 << DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT)
+#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_ENABLE	(1)
 #define DC_WIN_A_BYTE_SWAP_0			0x701
 #define DC_WIN_A_BUFFER_CONTROL_0		0x702
 #define DC_WIN_A_COLOR_DEPTH_0			0x703
@@ -59,6 +62,7 @@
 #define DC_WIN_A_BLEND_MATCH_SELECT_0		0x717
 #define DC_WIN_A_BLEND_NOMATCH_SELECT_0		0x718
 #define DC_WIN_A_BLEND_ALPHA_1BIT_0		0x719
+#define DC_WINBUF_A_START_ADDR_LO_0		0x800
 #define DC_WINBUF_A_START_ADDR_HI_0		0x80d
 #define DC_WINBUF_A_ADDR_H_OFFSET_0		0x806
 #define DC_WINBUF_A_ADDR_V_OFFSET_0		0x808
@@ -177,9 +181,18 @@
 /* ardpaux.h */
 #define DPAUX_DP_AUXDATA_READ_W0				0x19
 
+#define DP_LVDS_SHIFT	25
+#define DP_LVDS		(1 << DP_LVDS_SHIFT)
+
+#define SRC_BPP		16
+#define COLORDEPTH	0x6
+#define COLOR_WHITE	0xFFFFFF
+
 void setup_display(struct soc_nvidia_tegra124_config *config);
 void init_dca_regs(void);
-void init_dpaux_regs(void);
-void init_sor_regs(void);
 void dp_io_powerup(void);
+u32 dp_setup_timing(u32 width, u32 height);
+void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
+		     u32 lane_count, u32 enhanced_framing, u32 panel_edp,
+		     u32 pclkfreq, u32 linkfreq);
 #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ */