tegra124/nyan: memory and display updates

tegra124: use pll_c_out1 as sclk parent
Reviewed-on: https://chromium-review.googlesource.com/180865
(cherry picked from commit 418337a5bde70df6a770222201c51bf3e8892d5f)

tegra124: take LP cluster out of reset
Reviewed-on: https://chromium-review.googlesource.com/180866
(cherry picked from commit 74cdc68ea9b29da9af313635787e82bacb9e23e3)

tegra124: norrin: display code clean up
Reviewed-on: https://chromium-review.googlesource.com/181003
(cherry picked from commit 63843ec61b3b47ffc985edcb589771591c5c9f17)

tegra124: Change the display hack to use window A
Reviewed-on: https://chromium-review.googlesource.com/182001
(cherry picked from commit ef245e42eb17b2eb0e8712f252353a95ee6fc01a)

tegra124: norrin: Initialize frame buffer
Reviewed-on: https://chromium-review.googlesource.com/182090
(cherry picked from commit b7c1d1b3c9519cbbe1615737aed4c4c0efed2167)

nyan: do not enable pull-ups on SPI1 (EC) data pins
Reviewed-on: https://chromium-review.googlesource.com/181063
(cherry picked from commit 2f55188501ebcae9e01b12831f152d4520c7047c)

tegra124: Add source for the LP0 resume blob.
Reviewed-on: https://chromium-review.googlesource.com/183152
(cherry picked from commit a00d099bf710c297320d7edff7f7c608283d1b0b)

tegra124: Revise Memory Controller registers structure definition.
Reviewed-on: https://chromium-review.googlesource.com/182992
(cherry picked from commit ae83564cdd1d46c8166df1a95703e8cb1060c0a1)

tegra124: Add more PMC register details.
Reviewed-on: https://chromium-review.googlesource.com/183231
(cherry picked from commit d62ed2c19693284f10c2a12f4295091de3ace829)

tegra124: Add SDRAM configuration header file from cbootimage.
Reviewed-on: https://chromium-review.googlesource.com/182613
(cherry picked from commit 193ed2a104af38f6c41a332a649ce06a3238e0a4)

tegra124: Revise sdram_param.h for Coreboot.
Reviewed-on: https://chromium-review.googlesource.com/182614
(cherry picked from commit 311b0568c5de627435a5b035a7a1e40ecc2672f8)

tegra124: Fix EMC base address.
Reviewed-on: https://chromium-review.googlesource.com/183602
(cherry picked from commit 587c8969292ccecfa29c7720bcf24c704ed4ac4e)

tegra124: Add EMC registers definition.
Reviewed-on: https://chromium-review.googlesource.com/183622
(cherry picked from commit 67a8e5c7e87a1cc6bf006ad806751b549ffd3d5a)

tegra124: Never touch MEM(MC)/EMC clocks in ramstage.
Reviewed-on: https://chromium-review.googlesource.com/183623
(cherry picked from commit 8e3bb34d4ae37feae89b4a39850b2988a334d023)

tegra124: use RAM_CODE[3:2] for ram code
Reviewed-on: https://chromium-review.googlesource.com/183833
(cherry picked from commit 0154239467064ffcbdb82fc4c6b629f5d0c3568d)

tegra124: Allow setting PLLM (clock for SDRAM).
Reviewed-on: https://chromium-review.googlesource.com/183621
(cherry picked from commit a534e5b7c61d655eedd409dbd7780a4f90d40683)

tegra124: SDRAM Initialization.
Reviewed-on: https://chromium-review.googlesource.com/182615
(cherry picked from commit 5a60ae93b0603ee0d4806132be0360f3b1612bce)

tegra124: Get RAM_CODE for SDRAM initialization.
Reviewed-on: https://chromium-review.googlesource.com/183781
(cherry picked from commit a5b7ce70525d7ffef3fac90b8eb14b3f3787f4d8)

Squashed 18 nyan/tegra commits for memory and display.

Change-Id: I59a781ee8dc2fd9c9085373f5a9bb7c8108b094c
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6914
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

1 files changed, 93 insertions, 104 deletions

diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c
index 32056991fb..6b0f4c8698 100644
--- a/src/soc/nvidia/tegra124/dp.c
+++ b/src/soc/nvidia/tegra124/dp.c
@@ -39,33 +39,36 @@ static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
 }
 
 static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
-									  u32 reg, u32 val)
+					  u32 reg, u32 val)
 {
 	void *addr = dp->aux_base + (u32) (reg << 2);
 	WRITEL(val, addr);
 }
 
 static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
-											   u32 reg, u32 mask, u32 exp_val,
-											   u32 poll_interval_us,
-											   u32 timeout_ms)
+					   u32 reg, u32 mask, u32 exp_val,
+					   u32 poll_interval_us,
+					   u32 timeout_us)
 {
 	u32 reg_val = 0;
+	u32 temp = timeout_us;
 
-	printk(BIOS_SPEW, "JZ: %s: enter, poll_reg: %#x: timeout: 0x%x\n",
-		   __func__, reg * 4, timeout_ms);
 	do {
-		udelay(1);
+		udelay(poll_interval_us);
 		reg_val = tegra_dpaux_readl(dp, reg);
-	} while (((reg_val & mask) != exp_val) && (--timeout_ms > 0));
+		if (timeout_us > poll_interval_us)
+			timeout_us -= poll_interval_us;
+		else
+			break;
+	} while ((reg_val & mask) != exp_val);
 
 	if ((reg_val & mask) == exp_val)
 		return 0;	/* success */
-	printk(BIOS_SPEW,
+	printk(BIOS_ERR,
 		   "dpaux_poll_register 0x%x: timeout: "
 		   "(reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
 		   reg, reg_val, mask, exp_val);
-	return timeout_ms;
+	return temp;
 }
 
 static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
@@ -73,18 +76,18 @@ static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
 	/* According to DP spec, each aux transaction needs to finish
 	   within 40ms. */
 	if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL,
-									 DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
-									 DPAUX_DP_AUXCTL_TRANSACTREQ_DONE,
-									 100, DP_AUX_TIMEOUT_MS * 1000) != 0) {
-		printk(BIOS_SPEW, "dp: DPAUX transaction timeout\n");
+					 DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
+					 DPAUX_DP_AUXCTL_TRANSACTREQ_DONE,
+					 100, DP_AUX_TIMEOUT_MS * 1000) != 0) {
+		printk(BIOS_INFO, "dp: DPAUX transaction timeout\n");
 		return -1;
 	}
 	return 0;
 }
 
 static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
-									  u32 addr, u8 * data, u32 * size,
-									  u32 * aux_stat)
+					  u32 addr, u8 *data, u32 *size,
+					  u32 *aux_stat)
 {
 	int i;
 	u32 reg_val;
@@ -102,21 +105,11 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
 		case DPAUX_DP_AUXCTL_CMD_AUXWR:
 			break;
 		default:
-			printk(BIOS_SPEW, "dp: aux write cmd 0x%x is invalid\n", cmd);
+			printk(BIOS_ERR, "dp: aux write cmd 0x%x is invalid\n",
+				cmd);
 			return -1;
 	}
 
-#if 0
-/* interesting. */
-	if (tegra_platform_is_silicon()) {
-		*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
-		if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
-			printk(BIOS_SPEW, "dp: HPD is not detected\n");
-			return -EFAULT;
-		}
-	}
-#endif
-
 	tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
 	for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) {
 		memcpy(&temp_data, data, 4);
@@ -139,7 +132,7 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
 		tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
 
 		if (tegra_dpaux_wait_transaction(dp))
-			printk(BIOS_SPEW, "dp: aux write transaction timeout\n");
+			printk(BIOS_ERR, "dp: aux write transaction timeout\n");
 
 		*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
 
@@ -148,13 +141,13 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
 			(*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
 			(*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
 			if (timeout_retries-- > 0) {
-				printk(BIOS_SPEW, "dp: aux write retry (0x%x) -- %d\n",
+				printk(BIOS_INFO, "dp: aux write retry (0x%x) -- %d\n",
 					   *aux_stat, timeout_retries);
 				/* clear the error bits */
 				tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat);
 				continue;
 			} else {
-				printk(BIOS_SPEW, "dp: aux write got error (0x%x)\n",
+				printk(BIOS_ERR, "dp: aux write got error (0x%x)\n",
 					   *aux_stat);
 				return -1;
 			}
@@ -163,13 +156,13 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
 		if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
 			(*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
 			if (defer_retries-- > 0) {
-				printk(BIOS_SPEW, "dp: aux write defer (0x%x) -- %d\n",
+				printk(BIOS_INFO, "dp: aux write defer (0x%x) -- %d\n",
 					   *aux_stat, defer_retries);
 				/* clear the error bits */
 				tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat);
 				continue;
 			} else {
-				printk(BIOS_SPEW, "dp: aux write defer exceeds max retries "
+				printk(BIOS_ERR, "dp: aux write defer exceeds max retries "
 					   "(0x%x)\n", *aux_stat);
 				return -1;
 			}
@@ -180,7 +173,8 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
 			*size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
 			return 0;
 		} else {
-			printk(BIOS_SPEW, "dp: aux write failed (0x%x)\n", *aux_stat);
+			printk(BIOS_ERR, "dp: aux write failed (0x%x)\n",
+				*aux_stat);
 			return -1;
 		}
 	}
@@ -189,7 +183,7 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
 }
 
 static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
-								u8 * data, u32 * size, u32 * aux_stat)
+					u8 *data, u32 *size, u32 *aux_stat)
 {
 	u32 cur_size = 0;
 	u32 finished = 0;
@@ -202,7 +196,7 @@ static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
 			cur_size = DP_AUX_MAX_BYTES;
 		cur_left = cur_size;
 		ret = tegra_dc_dpaux_write_chunk(dp, cmd, addr,
-										 data, &cur_left, aux_stat);
+						 data, &cur_left, aux_stat);
 
 		cur_size -= cur_left;
 		finished += cur_size;
@@ -218,8 +212,8 @@ static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
 }
 
 static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
-									 u32 addr, u8 * data, u32 * size,
-									 u32 * aux_stat)
+					 u32 addr, u8 *data, u32 *size,
+					 u32 *aux_stat)
 {
 	u32 reg_val;
 	u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
@@ -236,7 +230,8 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
 		case DPAUX_DP_AUXCTL_CMD_AUXRD:
 			break;
 		default:
-			printk(BIOS_SPEW, "dp: aux read cmd 0x%x is invalid\n", cmd);
+			printk(BIOS_ERR, "dp: aux read cmd 0x%x is invalid\n",
+				cmd);
 			return -1;
 	}
 
@@ -253,37 +248,38 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
 	reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
 	reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
 	reg_val |= cmd;
-	printk(BIOS_SPEW, "cmd = %08x\n", reg_val);
 	reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
 	reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
-	printk(BIOS_SPEW, "cmd = %08x\n", reg_val);
 	while ((timeout_retries > 0) && (defer_retries > 0)) {
 		if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
 			(defer_retries != DP_AUX_DEFER_MAX_TRIES))
 			udelay(DP_DPCP_RETRY_SLEEP_NS * 2);
 
 		reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
-		printk(BIOS_SPEW, "cmd = %08x\n", reg_val);
 		tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
 
 		if (tegra_dpaux_wait_transaction(dp))
-			printk(BIOS_SPEW, "dp: aux read transaction timeout\n");
+			printk(BIOS_INFO, "dp: aux read transaction timeout\n");
 
 		*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
-		printk(BIOS_SPEW, "dp: %s: aux stat: 0x%08x\n", __func__, *aux_stat);
+		printk(BIOS_DEBUG, "dp: %s: aux stat: 0x%08x\n", __func__,
+				*aux_stat);
 
 		if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
 			(*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
 			(*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
 			(*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
 			if (timeout_retries-- > 0) {
-				printk(BIOS_SPEW, "dp: aux read retry (0x%x) -- %d\n",
-					   *aux_stat, timeout_retries);
+				printk(BIOS_INFO, "dp: aux read retry (0x%x)"
+						" -- %d\n", *aux_stat,
+						timeout_retries);
 				/* clear the error bits */
-				tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat);
+				tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
+						*aux_stat);
 				continue;	/* retry */
 			} else {
-				printk(BIOS_SPEW, "dp: aux read got error (0x%x)\n", *aux_stat);
+				printk(BIOS_ERR, "dp: aux read got error"
+						" (0x%x)\n", *aux_stat);
 				return -1;
 			}
 		}
@@ -291,13 +287,13 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
 		if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
 			(*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
 			if (defer_retries-- > 0) {
-				printk(BIOS_SPEW, "dp: aux read defer (0x%x) -- %d\n",
+				printk(BIOS_INFO, "dp: aux read defer (0x%x) -- %d\n",
 					   *aux_stat, defer_retries);
 				/* clear the error bits */
 				tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat);
 				continue;
 			} else {
-				printk(BIOS_SPEW, "dp: aux read defer exceeds max retries "
+				printk(BIOS_INFO, "dp: aux read defer exceeds max retries "
 					   "(0x%x)\n", *aux_stat);
 				return -1;
 			}
@@ -310,20 +306,22 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
 
 			for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i)
 				temp_data[i] = tegra_dpaux_readl(dp,
-												 DPAUX_DP_AUXDATA_READ_W(i));
+						DPAUX_DP_AUXDATA_READ_W(i));
 
 			*size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
-			printk(BIOS_SPEW, "dp: aux read data %d bytes\n", *size);
+			printk(BIOS_INFO, "dp: aux read data %d bytes\n",
+					*size);
 			memcpy(data, temp_data, *size);
 
 			return 0;
 		} else {
-			printk(BIOS_SPEW, "dp: aux read failed (0x%x\n", *aux_stat);
+			printk(BIOS_ERR, "dp: aux read failed (0x%x\n",
+					*aux_stat);
 			return -1;
 		}
 	}
 	/* Should never come to here */
-	printk(BIOS_SPEW, "%s: can't\n", __func__);
+	printk(BIOS_ERR, "%s: can't\n", __func__);
 	return -1;
 }
 
@@ -340,7 +338,7 @@ int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
 			cur_size = DP_AUX_MAX_BYTES;
 
 		ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr,
-										data, &cur_size, aux_stat);
+						data, &cur_size, aux_stat);
 
 		/* cur_size should be the real size returned */
 		addr += cur_size;
@@ -350,12 +348,6 @@ int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
 		if (ret)
 			break;
 
-#if 0
-		if (cur_size == 0) {
-			printk(BIOS_SPEW, "JZ: no data found, ret\n");
-			break;
-		}
-#endif
 	} while (*size > finished);
 
 	*size = finished;
@@ -372,7 +364,7 @@ static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
 	ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
 									cmd, data_ptr, &size, &status);
 	if (ret)
-		printk(BIOS_SPEW,
+		printk(BIOS_ERR,
 			   "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n", cmd,
 			   status);
 
@@ -380,7 +372,7 @@ static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
 }
 
 static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
-										 struct tegra_dc_dp_link_config *cfg)
+					 struct tegra_dc_dp_link_config *cfg)
 {
 	u8 dpcd_data;
 	int ret;
@@ -390,27 +382,26 @@ static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
 		return ret;
 
 	cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
-	printk(BIOS_SPEW, "JZ: %s: max_lane_count: %d\n", __func__,
+	printk(BIOS_INFO, "%s: max_lane_count: %d\n", __func__,
 		   cfg->max_lane_count);
 
 	cfg->support_enhanced_framing =
 		(dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ? 1 : 0;
-	printk(BIOS_SPEW, "JZ: %s: enh-framing: %d\n", __func__,
+	printk(BIOS_INFO, "%s: enh-framing: %d\n", __func__,
 		   cfg->support_enhanced_framing);
 
 	ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD, &dpcd_data);
 	if (ret)
 		return ret;
 	cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ? 1 : 0;
-	printk(BIOS_SPEW, "JZ: %s: downspread: %d\n", __func__, cfg->downspread);
+	printk(BIOS_INFO, "%s: downspread: %d\n", __func__, cfg->downspread);
 
 	ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
 								&cfg->max_link_bw);
 	if (ret)
 		return ret;
-	printk(BIOS_SPEW, "JZ: %s: max_link_bw: %d\n", __func__, cfg->max_link_bw);
+	printk(BIOS_INFO, "%s: max_link_bw: %d\n", __func__, cfg->max_link_bw);
 
-	// jz, changed
 	// cfg->bits_per_pixel = dp->dc->pdata->default_out->depth;
 	cfg->bits_per_pixel = 18;
 
@@ -427,7 +418,7 @@ static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
 		(dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ? 1 : 0;
 	cfg->only_enhanced_framing =
 		(dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ? 1 : 0;
-	printk(BIOS_SPEW, "JZ: %s: alt_reset_cap: %d, only_enh_framing: %d\n",
+	printk(BIOS_DEBUG, "%s: alt_reset_cap: %d, only_enh_framing: %d\n",
 		   __func__, cfg->alt_scramber_reset_cap, cfg->only_enhanced_framing);
 
 	cfg->lane_count = cfg->max_lane_count;
@@ -448,13 +439,13 @@ static int tegra_dc_dpcd_read_rev(struct tegra_dc_dp_data *dp, u8 * rev)
 	ret = tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
 							  NV_DPCD_REV, rev, &size, &status);
 	if (ret) {
-		printk(BIOS_SPEW, "dp: Failed to read NV_DPCD_REV\n");
+		printk(BIOS_WARNING, "dp: Failed to read NV_DPCD_REV\n");
 		return ret;
 	}
 	return 0;
 }
 
-u32 dp_setup_timing(u32 panel_id, u32 width, u32 height);
+u32 dp_setup_timing(u32 width, u32 height);
 void dp_bringup(u32 winb_addr)
 {
 	struct tegra_dc_dp_data *dp = &dp_data;
@@ -465,40 +456,40 @@ void dp_bringup(u32 winb_addr)
 	u32 xres = 1366;	/* norrin display */
 	u32 yres = 768;
 
-	printk(BIOS_SPEW, "JZ: %s: entry\n", __func__);
-
 	dp->sor.base = (void *)TEGRA_ARM_SOR;
 	dp->sor.portnum = 0;
 
 	dp->aux_base = (void *)TEGRA_ARM_DPAUX;
 
 	/* read panel info */
-	if (!tegra_dc_dpcd_read_rev(dp, (u8 *) & dpcd_rev)) {
-		printk(BIOS_SPEW, "PANEL info: \n");
-		printk(BIOS_SPEW, "--DPCP version(%#x): %d.%d\n",
-			   dpcd_rev, (dpcd_rev >> 4) & 0x0f, (dpcd_rev & 0x0f));
+	if (!tegra_dc_dpcd_read_rev(dp, (u8 *)&dpcd_rev)) {
+		printk(BIOS_INFO, "PANEL info:\n");
+		printk(BIOS_INFO, "--DPCP version(%#x): %d.%d\n",
+				dpcd_rev, (dpcd_rev >> 4) & 0x0f,
+				(dpcd_rev & 0x0f));
 	}
 
 	if (tegra_dc_dp_init_max_link_cfg(dp, &dp->link_cfg))
-		printk(BIOS_SPEW, "dp: failed to init link configuration\n");
+		printk(BIOS_ERR, "dp: failed to init link configuration\n");
 
 	dp_link_training((u32) (dp->link_cfg.lane_count),
 					 (u32) (dp->link_cfg.link_bw));
 
-	pclk_freq = dp_setup_timing(5, xres, yres);
-	printk(BIOS_SPEW, "JZ: %s: pclk_freq: %d\n", __func__, pclk_freq);
+	pclk_freq = dp_setup_timing(xres, yres);
+	printk(BIOS_DEBUG, "%s: pclk_freq: %d\n", __func__, pclk_freq);
 
-	void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
-						 u32 lane_count, u32 enhanced_framing, u32 panel_edp,
-						 u32 pclkfreq, u32 linkfreq);
 
-	dp_misc_setting(dp->link_cfg.bits_per_pixel,
-					xres, yres, winb_addr,
-					(u32) dp->link_cfg.lane_count,
-					(u32) dp->link_cfg.enhanced_framing,
-					(u32) dp->link_cfg.alt_scramber_reset_cap,
-					pclk_freq, dp->link_cfg.link_bw * 27);
+	void dp_misc_setting(u32 panel_bpp, u32 width, u32 height,
+				u32 winb_addr, u32 lane_count,
+				u32 enhanced_framing, u32 panel_edp,
+				u32 pclkfreq, u32 linkfreq);
 
+	dp_misc_setting(dp->link_cfg.bits_per_pixel,
+				xres, yres, winb_addr,
+				(u32) dp->link_cfg.lane_count,
+				(u32) dp->link_cfg.enhanced_framing,
+				(u32) dp->link_cfg.alt_scramber_reset_cap,
+				pclk_freq, dp->link_cfg.link_bw * 27);
 }
 
 void debug_dpaux_print(u32 addr, u32 size)
@@ -509,21 +500,22 @@ void debug_dpaux_print(u32 addr, u32 size)
 	int i;
 
 	if ((size == 0) || (size > 16)) {
-		printk(BIOS_SPEW, "dp: %s: invalid size %d\n", __func__, size);
+		printk(BIOS_ERR, "dp: %s: invalid size %d\n", __func__, size);
 		return;
 	}
 
 	if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
-							addr, buf, &size, &status)) {
-		printk(BIOS_SPEW, "******AuxRead Error: 0x%04x: status 0x%08x\n", addr,
-			   status);
+				addr, buf, &size, &status)) {
+		printk(BIOS_ERR, "******AuxRead Error: 0x%04x: status 0x%08x\n",
+				addr, status);
 		return;
 	}
-	printk(BIOS_SPEW, "%s: addr: 0x%04x, size: %d\n", __func__, addr, size);
+	printk(BIOS_DEBUG, "%s: addr: 0x%04x, size: %d\n", __func__,
+			addr, size);
 	for (i = 0; i < size; ++i)
-		printk(BIOS_SPEW, " %02x", buf[i]);
+		printk(BIOS_DEBUG, " %02x", buf[i]);
 
-	printk(BIOS_SPEW, "\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 int dpaux_read(u32 addr, u32 size, u8 * data)
@@ -533,14 +525,14 @@ int dpaux_read(u32 addr, u32 size, u8 * data)
 	u32 status = 0;
 
 	if ((size == 0) || (size > 16)) {
-		printk(BIOS_SPEW, "dp: %s: invalid size %d\n", __func__, size);
+		printk(BIOS_ERR, "dp: %s: invalid size %d\n", __func__, size);
 		return -1;
 	}
 
 	if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
-							addr, data, &size, &status)) {
-		printk(BIOS_SPEW, "dp: Failed to read reg %#x, status: %#x\n", addr,
-			   status);
+					addr, data, &size, &status)) {
+		printk(BIOS_ERR, "dp: Failed to read reg %#x, status: %#x\n",
+				addr, status);
 		return -1;
 	}
 
@@ -553,13 +545,10 @@ int dpaux_write(u32 addr, u32 size, u32 data)
 	u32 status = 0;
 	int ret;
 
-	printk(BIOS_SPEW, "JZ: %s: entry, addr: 0x%08x, size: 0x%08x, data: %#x\n",
-		   __func__, addr, size, data);
-
 	ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
 							   addr, (u8 *) & data, &size, &status);
 	if (ret)
-		printk(BIOS_SPEW, "dp: Failed to write to reg %#x, status: 0x%x\n",
+		printk(BIOS_ERR, "dp: Failed to write to reg %#x, status: 0x%x\n",
 			   addr, status);
 	return ret;
 }