diff options
| author | Vince Hsu <vinceh@nvidia.com> | 2014-06-11 17:14:05 +0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-01-04 00:14:03 +0100 |
| commit | 1e3679ddd0fd03fdc00b50a45fc652a539b9c9a7 (patch) | |
| tree | 11020367ea7d724801654a7e3f7b017048b393ce /src/soc/nvidia/tegra124/display.c | |
| parent | c1f7cbe49f0023655f6f60b1d924ed5c61533806 (diff) | |
tegra124: configure DP with correct pixel clock
For some panels, the plld can't provide the pixel clock that
the panels wants, so we give it a good enough one. And we
should calculate the dp/dc settings by the real pixel clock.
BRANCH=nyan
BUG=chrome-os-partner:29489
TEST=Verified the panels N116BGE-EA2(Nyan) and N133BGE-EAB(Big).
No screen flicker is observed. No sor dp fifo underflow found.
Original-Change-Id: I037b2bd5f5e9bb8b15ab6f47a84ac7ef2e207779
Original-Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203358
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit d320f0c6b54ea8ca84206447b223da76ac5f771b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I772bb8e7a40cc462c72ba0fb9657c63ed2e0d0ac
Reviewed-on: http://review.coreboot.org/8044
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra124/display.c')
| -rw-r--r-- | src/soc/nvidia/tegra124/display.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 9ad76f0ead..6f6790d56e 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -221,6 +221,7 @@ void display_startup(device_t dev) struct display_controller *disp_ctrl = (void *)config->display_controller; struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE; struct tegra_dc *dc = &dc_data; + u32 plld_rate; /* init dc */ dc->base = (void *)TEGRA_ARM_DISPLAYA; @@ -282,10 +283,14 @@ void display_startup(device_t dev) * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the * update_display_mode() for detail. */ - if (clock_display(config->pixel_clock * 2)) { + plld_rate = clock_display(config->pixel_clock * 2); + if (plld_rate == 0) { printk(BIOS_ERR, "dc: clock init failed\n"); return; - }; + } else if (plld_rate != config->pixel_clock * 2) { + printk(BIOS_WARNING, "dc: plld rounded to %u\n", plld_rate); + config->pixel_clock = plld_rate / 2; + } /* Init dc */ if (tegra_dc_init(disp_ctrl)) { |