tegra124: Add some functions for resetting peripherals.

These make it possible to reset peripherals without having to dig into the
crc.

BUG=chrome-os-partner:27220
TEST=Built and booted on nyan with EFS and with the TPM bus turned up to
400KHz.
BRANCH=None

Original-Change-Id: I7e77b719e1ba30d2964cfbfda467f937d80b5b21
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/191810
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 18c6a48623ae6eff70ca05ea15a7901972a7bba3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8f46666bcf51215f332724ea871f14fec2b522f0
Reviewed-on: http://review.coreboot.org/7458
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

1 files changed, 42 insertions, 0 deletions

diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index cef4262f99..a81cf5f05a 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -531,3 +531,45 @@ void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
 	if (w) writel(w, &clk_rst->rst_dev_w_clr);
 	if (x) writel(x, &clk_rst->rst_dev_x_clr);
 }
+
+void clock_reset_l(u32 bit)
+{
+	writel(bit, &clk_rst->rst_dev_l_set);
+	udelay(1);
+	writel(bit, &clk_rst->rst_dev_l_clr);
+}
+
+void clock_reset_h(u32 bit)
+{
+	writel(bit, &clk_rst->rst_dev_h_set);
+	udelay(1);
+	writel(bit, &clk_rst->rst_dev_h_clr);
+}
+
+void clock_reset_u(u32 bit)
+{
+	writel(bit, &clk_rst->rst_dev_u_set);
+	udelay(1);
+	writel(bit, &clk_rst->rst_dev_u_clr);
+}
+
+void clock_reset_v(u32 bit)
+{
+	writel(bit, &clk_rst->rst_dev_v_set);
+	udelay(1);
+	writel(bit, &clk_rst->rst_dev_v_clr);
+}
+
+void clock_reset_w(u32 bit)
+{
+	writel(bit, &clk_rst->rst_dev_w_set);
+	udelay(1);
+	writel(bit, &clk_rst->rst_dev_w_clr);
+}
+
+void clock_reset_x(u32 bit)
+{
+	writel(bit, &clk_rst->rst_dev_x_set);
+	udelay(1);
+	writel(bit, &clk_rst->rst_dev_x_clr);
+}