diff options
author | Aaron Durbin <adurbin@chromium.org> | 2014-07-21 14:24:42 -0500 |
---|---|---|
committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-13 00:15:55 +0100 |
commit | 7ddb5f76feea37ed055f2eede944c2971214e2f2 (patch) | |
tree | d4cbb8e52e4a7b6198e96e8dda64803726607ea2 /src/soc/nvidia/tegra124/clock.c | |
parent | da9b9f324b7c4aea46c55bdbd1365a018791ee18 (diff) |
tegra132: Add Trust Zone register access
The Trust Zone carveout registers are only accessible using
a secure access mode. The AVP runs as non-secure all the time.
In EL3 the CPU is in secure mode, but when the MMU is enabled
the page tables dictate if accesses to certain regions are
secure or not. However, ramstage is currently being loaded
into non-secure memory and the page tables will live in
non-secure memory as well. Therefore, handle all these
cases by providing global state which mirrors the TZ
register.
BUG=chrome-os-partner:30782
BRANCH=None
TEST=Built and ran through ramstage with the MMU enabled
Resources are read and set accordingly.
Original-Change-Id: Ib76b2641497a29ef2adb75934b2df55ecf0b3e78
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209061
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 0bcbdc56978f6ebe3e7d1b74ed2fd861e03bb562)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9c1beed443a48870ba190427e87caf90caf4ff6b
Reviewed-on: http://review.coreboot.org/8648
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/nvidia/tegra124/clock.c')
0 files changed, 0 insertions, 0 deletions