t124: Clean up display init functions

The existing display init functions were translated from a script. The new
code will play the same functions but are cleaner and readable and easier to
be ported to new panel.

BUG=none
TEST=build nyan and boot up kernel.

Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>

Original-Change-Id: Ic9983e57684a03e206efe3731968ec62905f4ee8
Original-Reviewed-on: https://chromium-review.googlesource.com/189518
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 5998f991ea3069d603443b93c2ebdcdcd04af961)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Squashed to pass abuild

nyan: Fix the build for big and blaze.

The display code for the tegra124 was cleaned up recently, but only the nyan
device tree was updated to match the new code, not big's or blaze's. This
change copies nyan's device tree over to those other two boards which will get
them building again. The settings may not be correct, but they'll be no less
correct than they were before. I also updated the copyright date for nyan.

BUG=none
TEST=Built for nyan, nyan_big, nyan_blaze. Booted on nyan_big and verified the
panel wasn't damaged by the new display code or settings.
BRANCH=None

Original-Change-Id: I75055a01f9402b3a9de9a787a9d3e737d25bb515
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/191364
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit ea235f23df31b4ca8006dcdf3628eed096e062b9)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Icdad74bf2d013c3677e1a3373b8f89fad99f616e
Reviewed-on: http://review.coreboot.org/7454
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

1 files changed, 31 insertions, 17 deletions

diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h
index b05bcc7cba..87d043a8ca 100644
--- a/src/soc/nvidia/tegra124/chip.h
+++ b/src/soc/nvidia/tegra124/chip.h
@@ -23,14 +23,19 @@
 #include <soc/addressmap.h>
 #include "gpio.h"
 
+#define EFAULT  1
+#define EINVAL  2
+
 /* this is a misuse of the device tree. We're going to let it go for now but
  * we should at minimum have a struct for the display controller, since
  * the chip supports two.
  */
 struct soc_nvidia_tegra124_config {
-	int xres;
-	int yres;
-	int framebuffer_bits_per_pixel;
+	u32 xres;
+	u32 yres;
+	u32 framebuffer_bits_per_pixel;
+	u32 color_depth;
+	u32 panel_bits_per_pixel;
 	int cache_policy;
 	/* there are two. It's not unimaginable that we might someday
 	 * have two of these structs in a single mainboard.
@@ -60,32 +65,41 @@ struct soc_nvidia_tegra124_config {
 	 * This is stated to be four timings in the
 	 * u-boot docs. In any event, in coreboot, we generally
 	 * only delay long enough to let the panel wake up and then
-	 * do the control operations -- meaming, for *coreboot*
+	 * do the control operations -- meaning, for *coreboot*
 	 * we probably only need the vdd_delay, but payloads may
 	 * need the other info.
 	 */
 	/* Delay before from power on asserting vdd */
-	int vdd_delay;
-        /* delay between panel_vdd-rise and data-rise*/
-	int vdd_data_delay;
-	/* delay between data-rise and backlight_vdd-rise */
-	int data_backlight_delay;
-	/* delay between backlight_vdd and pwm-rise */
-	int backlight_pwm_delay;
-	/* delay between pwm-rise and backlight_en-rise */
-	int pwm_backlight_en_delay;
-	/* display timing.
-	 * we have not found a dts in which these are set */
-	int href_to_sync; /* u-boot code says 'set to 1' */
+	int vdd_delay_ms;
+
+	/* Delay before HPD high */
+	int vdd_to_hpd_delay_ms;
+
+	int hpd_unplug_min_us;
+	int hpd_plug_min_us;
+        int hpd_irq_min_us;
+
+	int href_to_sync;
 	int hsync_width;
 	int hback_porch;
 	int hfront_porch;
-	int vref_to_sync; /* u-boot code says 'set to 1' */
+	int vref_to_sync;
 	int vsync_width;
 	int vback_porch;
 	int vfront_porch;
 
 	int pixel_clock;
+	int pll_div;;
+
+	/* The minimum link configuraton settings */
+	u32 lane_count;
+	u32 enhanced_framing;
+	u32 link_bw;
+	u32 drive_current;
+	u32 preemphasis;
+	u32 postcursor;
+
+	void *dc_data;
 };
 
 #endif /* __SOC_NVIDIA_TEGRA124_CHIP_H__ */