nyans: reduce code duplication in bootblock and romstages

this change reduces the code duplication of the bootblock and the romstages for
Nyans.

BUG=none
TEST=Built Nyan, Big, and Blaze. Ran faft on Blaze.
BRANCH=none
Original-Signed-off-by: dnojiri@chromium.org (Daisuke Nojiri)
Original-Change-Id: Ieb9dac3b061a2cf46c63afb2f31eb67ab391ea1a
Original-Reviewed-on: https://chromium-review.googlesource.com/214050
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>

(cherry picked from commit f3413d39458f03895fe4963a41285f71d81bcf5f)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I912f63b12321aa26a7add302fc8a6c4e607330ef
Reviewed-on: http://review.coreboot.org/8880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 66 insertions, 0 deletions

diff --git a/src/soc/nvidia/tegra124/cache.c b/src/soc/nvidia/tegra124/cache.c
new file mode 100644
index 0000000000..55e625478a
--- /dev/null
+++ b/src/soc/nvidia/tegra124/cache.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/cache.h>
+#include <stdint.h>
+#include "cache.h"
+
+enum {
+	L2CTLR_ECC_PARITY = 0x1 << 21,
+	L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
+	L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6,
+	L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0,
+	L2CTLR_DATA_RAM_LATENCY_CYCLES_3  = 2 << 0
+};
+
+enum {
+	L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27,
+	L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7,
+	L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3
+};
+
+/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */
+static void configure_l2ctlr(void)
+{
+	uint32_t val;
+
+	val = read_l2ctlr();
+	val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK);
+	val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 |
+			L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | L2CTLR_ECC_PARITY);
+	write_l2ctlr(val);
+}
+
+/* Configures L2 Auxiliary Control Register for Cortex A15. */
+static void configure_l2actlr(void)
+{
+	uint32_t val;
+
+	val = read_l2actlr();
+	val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL |
+			L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT |
+			L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE);
+	write_l2actlr(val);
+}
+
+void configure_l2_cache(void)
+{
+	configure_l2ctlr();
+	configure_l2actlr();
+}