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authorRizwan Qureshi <rizwan.qureshi@intel.com>2016-08-24 16:05:32 +0530
committerMartin Roth <martinroth@google.com>2016-08-31 17:39:05 +0200
commit4dfe13081922454e97e6b0f8d6532cd97c635b60 (patch)
tree6de04389a077cddbff70e76d2605e68246985ad4 /src/soc/nvidia/tegra124/bootblock.c
parent3156934bf8f059fb8ba14965b75ed0ccb56c79cb (diff)
driver/intel/fsp2.0: Add External stage cache region helper
If ramstage caching outside CBMEM is enabled i.e CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM, then a helper function to determine the caching region in SMM should be implemented. Add the same to FSP2.0 driver. FSP1.1 driver had the same implementation hence copied stage_cache.c. The SoC code should implement the smm_subregion to provide the base and size of the caching region within SMM. The fsp/memmap.h provides the prototype and we will reuse the same from FPS 1.1. Change-Id: I4412a710391dc0cee044b96403c50260c3534e6f Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16312 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/nvidia/tegra124/bootblock.c')
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