diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2014-09-04 09:55:34 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2015-03-24 14:48:04 +0100 |
| commit | efddcfbb52cd328ad2eb86d88cd306ac30294109 (patch) | |
| tree | 0cf0e5aff39826797f48a3f040be9d50ce3cdb73 /src/soc/nvidia/tegra124/Kconfig | |
| parent | 1b05d887d702fcf5ac704d2ee5257122a180694c (diff) | |
vboot2: separate verstage from bootblock
With CONFIG_RETURN_FROM_VERSTAGE false, the verstage loads the romstage over
the bootblock, then exits to the romstage. this is necessary for some SOC
(e.g. tegra124) which runs the bootblock on a different architecture.
With CONFIG_RETURN_FROM_VERSTAGE true, the verstage returns to the bootblock.
Then, the bootblock loads the romstage over the verstage and exits to the
romstage. this is probably necessary for some SOC (e.g. rockchip) which does not
have SRAM big enough to fit the verstage and the romstage at the same time.
BUG=none
TEST=Built Blaze with USE=+/-vboot2. Ran faft on Blaze.
BRANCH=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I673945c5e21afc800d523fbb25d49fdc83693544
Original-Reviewed-on: https://chromium-review.googlesource.com/212365
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Note: This purposefully is probably broken in vendorcode/google/chromeos
as I'm just trying to set a base for dropping more patches in. The vboot
paths will have to change from how they are currently constructed.
(cherry picked from commit 4fa17395113d86445660091413ecb005485f8014)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I9117434ce99695f9b7021a06196d864f180df5c9
Reviewed-on: http://review.coreboot.org/8881
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra124/Kconfig')
| -rw-r--r-- | src/soc/nvidia/tegra124/Kconfig | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index fddb6dadab..4fcc6b4440 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -38,6 +38,16 @@ config BOOTBLOCK_CPU_INIT # 0x4002_0000 Bootblock (max 48KB). # 0x4002_C000 ROM stage (max 80KB). # 0x4003_FFFF End of iRAM. +# +# if VBOOT2_VERIFY_FIRMWARE, +# 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE. +# 0x4000_4020 CBMEM console area (8K-32B) +# 0x4000_6000 CBFS mapping cache (72K) +# 0x4001_8000 vboot work buffer (16K) +# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!). +# 0x4002_0000 bootblock and romstage (max 70KB). +# 0x4003_1000 verstage (max 60KB). +# 0x4003_FFFF End of iRAM. config BOOTBLOCK_ROM_OFFSET hex @@ -45,12 +55,10 @@ config BOOTBLOCK_ROM_OFFSET config CBFS_HEADER_ROM_OFFSET hex "offset of master CBFS header in ROM" - default 0x1e000 if VBOOT2_VERIFY_FIRMWARE default 0x18000 config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" - default 0x1e080 if VBOOT2_VERIFY_FIRMWARE default 0x18080 config SYS_SDRAM_BASE @@ -61,9 +69,16 @@ config BOOTBLOCK_BASE hex default 0x40020000 +# this has to be big enough to leave room big enough for the larger of the +# bootblock and the romstage. +config VERSTAGE_BASE + hex + default 0x40031000 + +# with vboot2, romstage is loaded over to the bootblock space config ROMSTAGE_BASE hex - default 0x4002d000 if VBOOT2_VERIFY_FIRMWARE + default 0x40020000 if VBOOT2_VERIFY_FIRMWARE default 0x4002c000 config RAMSTAGE_BASE @@ -94,7 +109,8 @@ config CBFS_CACHE_ADDRESS config CBFS_CACHE_SIZE hex "size of CBFS cache data" - default 0x00017fe0 + default 0x00012000 if VBOOT2_VERIFY_FIRMWARE + default 0x00016000 config VBOOT_WORK_BUFFER_ADDRESS hex "memory address of vboot work buffer" |