tegra/nyan*: sdram updates

nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU
Reviewed-on: https://chromium-review.googlesource.com/183939
(cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1)

nyan_big: Add initial 792MHz BCT
Reviewed-on: https://chromium-review.googlesource.com/183975
(cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a)

nyan_big: use RAM_CODE[3:2] for ram code
Reviewed-on: https://chromium-review.googlesource.com/184076
(cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716)

tegra124: support tri-state Board Id
Reviewed-on: https://chromium-review.googlesource.com/183855
(cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4)

nyan*: Fix SPI pinmux configuration
Reviewed-on: https://chromium-review.googlesource.com/184281
(cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489)

nyan_big: Add 4GB 204/792MHz BCTs
Reviewed-on: https://chromium-review.googlesource.com/184159
(cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e)

tegra124: Add function for obtaining DRAM size via MC regs
Reviewed-on: https://chromium-review.googlesource.com/184535
(cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48)

tegra124/nyan*: Obtain DRAM size dynamically
Reviewed-on: https://chromium-review.googlesource.com/184431
(cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3)

tegra124: Rearrange iRAM layout to allow more space for romstage
Reviewed-on: https://chromium-review.googlesource.com/184240
(cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc)

tegra124: Fix MemoryType field name in SDRAM parameters.
Reviewed-on: https://chromium-review.googlesource.com/185113
(cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97)

nyan_big: Initialize SDRAM without BootROM.
Reviewed-on: https://chromium-review.googlesource.com/183624
(cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70)

tegra124: move FB_SIZE_MB to a more appropriate location
Reviewed-on: https://chromium-review.googlesource.com/184930
(cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc)

nyan: Initialize SDRAM without BootROM.
Reviewed-on: https://chromium-review.googlesource.com/185114
(cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b)

tegra124: Save SDRAM parameters to PMC registers for LP0
Reviewed-on: https://chromium-review.googlesource.com/182928
(cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86)

tegra124: Rewrite SDRAM parameter saving code to be more efficient
Reviewed-on: https://chromium-review.googlesource.com/184388
(cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6)

nyan: Slightly change the way SDRAM parameter files are set up
Reviewed-on: https://chromium-review.googlesource.com/185286
(cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d)

Squashed 16 commits for SDRAM support on nyan and nyan_big.

Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6949
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

1 files changed, 16 insertions, 17 deletions

diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index ec6ee92ea3..3876a9e39c 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -26,17 +26,15 @@ config BOOTBLOCK_CPU_INIT
 # 0x18080 Free for CBFS data.
 #
 # iRAM (256k) layout.
-# 0x4000_0000 BootROM runtime data/stack area, can be reclaimed after BootROM.
-#       +0000 (BootROM) Boot Information Table.
-#       +0100 (BootROM) BCT.
-#       ---------------------------------------------------------------------
-#       +0000 (Coreboot) TTB 16KB.
-#       +4000 (Coreboot) Stack.
-# 0x4000_E000 Valid for anything to be executed after BootROM (effective entry
-#             point address specified in BCT).
-#       +0000 (Coreboot) Bootblock (max 36k).
-#       +9000 (Coreboot) ROM stage (max 36k).
-# 0x4002_0000 (Coreboot) Cache of CBFS.
+# (Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
+#  so the bootblock loading address must be placed after that. After the
+#  handoff that area may be reclaimed for other uses, e.g. CBFS cache.)
+#
+# 0x4000_0000 TTB (16KB).
+# 0x4000_4000 CBFS mapping cache (96KB).
+# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!).
+# 0x4002_0000 Bootblock (max 48KB).
+# 0x4002_C000 ROM stage (max 80KB).
 # 0x4003_FFFF End of iRAM.
 
 config BOOTBLOCK_ROM_OFFSET
@@ -57,11 +55,11 @@ config SYS_SDRAM_BASE
 
 config BOOTBLOCK_BASE
 	hex
-	default 0x4000e000
+	default 0x40020000
 
 config ROMSTAGE_BASE
 	hex
-	default 0x40017000
+	default 0x4002c000
 
 config RAMSTAGE_BASE
 	hex
@@ -69,12 +67,13 @@ config RAMSTAGE_BASE
 
 config STACK_TOP
 	hex
-	default 0x4000c000
+	default 0x40020000
 
 config STACK_BOTTOM
 	hex
-	default 0x40004000
+	default 0x4001c000
 
+# This is the ramstage thread stack, *not* the same as above! Currently unused.
 config STACK_SIZE
 	hex
 	default 0x800
@@ -86,10 +85,10 @@ config TTB_BUFFER
 
 config CBFS_CACHE_ADDRESS
 	hex "memory address to put CBFS cache data"
-	default 0x40020000
+	default 0x40004000
 
 config CBFS_CACHE_SIZE
 	hex "size of CBFS cache data"
-	default 0x00020000
+	default 0x00018000
 
 endif