tegra124/nyan: various fixes and additions

Tegra124: SDMMC: Configure base clock frequency.
Reviewed-on: https://chromium-review.googlesource.com/173841
(cherry picked from commit d3157e9a380cfb018cc69a1f23f277c3c5b680a6)

Tegra124: SDMMC: Configure pinmux for MMC 3/4.
Reviewed-on: https://chromium-review.googlesource.com/174011
(cherry picked from commit 55af9a86a56d6bc0ce9bcff4fd5226a60ae2033b)

tegra124: Move DMA-related #defines and definitions to header
Reviewed-on: https://chromium-review.googlesource.com/174444
(cherry picked from commit 9d917927a5b7151958289469b9049ac91efa41e3)

tegra124: Assign console address for kernel.
Reviewed-on: https://chromium-review.googlesource.com/174486
(cherry picked from commit 36e9370f30bd173879958d164156997841ec4e9c)

nyan: Fix up the gpio indices in chromeos.c.
Reviewed-on: https://chromium-review.googlesource.com/174418
(cherry picked from commit fba4ae1080c19f11abe1205b871ada14db996c61)

Nyan: turn on the backlight.
Reviewed-on: https://chromium-review.googlesource.com/174533
(cherry picked from commit 12649c9611981dd8d6567ba0238c8b8247c52215)

tegra124: Fix the disp1 source field.
Reviewed-on: https://chromium-review.googlesource.com/174701
(cherry picked from commit eed380e09075e1eef0bde7d1bb15c4343f30bfe0)

nyan: set up the aux channel i2c interface
Reviewed-on: https://chromium-review.googlesource.com/174620
(cherry picked from commit ea81cb44a1c11cd78643c69ac818304cd393749e)

tegra124: fix typos in the clock code.
Reviewed-on: https://chromium-review.googlesource.com/174684
(cherry picked from commit 72365c33693db4eb6e01032938221f592b7e5a02)

tegra124: Revamp clock source/divisor configuration
Reviewed-on: https://chromium-review.googlesource.com/174804
(cherry picked from commit 3f31a634f69595bcc6a473301d1492c97a767809)

tegra: Add gpio_output_open_drain() function
Reviewed-on: https://chromium-review.googlesource.com/174650
(cherry picked from commit bc1c28926810e722e9b82339ea0585d083e3fa8c)

tegra124: add nvidia-generated files
Reviewed-on: https://chromium-review.googlesource.com/174610
(cherry picked from commit 7706f3200f7fc11b7a443f336bff6a37afa94652)

nyan: Ignore the dev mode GPIO.
Reviewed-on: https://chromium-review.googlesource.com/174837
(cherry picked from commit 9513e608f3063fdb3e9d8bd04e6e5fe35a5bfcee)

Tegra124: Add support for the ARM architectural timer.
Reviewed-on: https://chromium-review.googlesource.com/174835
(cherry picked from commit 25a91fcf7e79cc450caa59bc6b65f954bb96ac6c)

nyan: Initialize the ARM architectural timer in the RAM stage.
Reviewed-on: https://chromium-review.googlesource.com/174836
(cherry picked from commit 581f592c12de91c0cf8279ede2850e38dd0cd2e8)

tegra124: nyan: Move mainboard level clock stuff into the mainboard source.
Reviewed-on: https://chromium-review.googlesource.com/174843
(cherry picked from commit 5ab100b0bad22814261f9b755b59394562c9145a)

tegra124: add some explanatory text about U7.1 computations.
Reviewed-on: https://chromium-review.googlesource.com/173910
(cherry picked from commit 822cad0ceeceeb5160c8216e05eec13fd04a6413)

Set the EC SPI clock source to PLLP and divide down to around 5MHz
Reviewed-on: https://chromium-review.googlesource.com/173954
(cherry picked from commit c0e22d76d3887ca1f727443a47db38dec12c0b74)

nyan: Move non-essential configuration out of bootblock and into ram stage.
Reviewed-on: https://chromium-review.googlesource.com/174844
(cherry picked from commit dad7f68c76f7b83edacd8b22c9dbd3f0ff027397)

tegra124: clocks: Save some IOs in clock_enable_clear_reset.
Reviewed-on: https://chromium-review.googlesource.com/174845
(cherry picked from commit 81b977a2758d42471667e2cbe31f160dfda5bca4)

tegra124: re-write SPI driver w/ full duplex support
Reviewed-on: https://chromium-review.googlesource.com/174446
(cherry picked from commit 51c9a34240d6a068780a7d1c27b032b56b2d3e54)

tegra124: move SPI-related structures from .c to .h
Reviewed-on: https://chromium-review.googlesource.com/174637
(cherry picked from commit 36760a4463c2c33f494ca7ea5a36810fa4502058)

tegra124: add frame header info to SPI channel struct
Reviewed-on: https://chromium-review.googlesource.com/174638
(cherry picked from commit e24773eb946e2c4cb5e828f055d45d92bd1a4f9f)

tegra124: re-factor tegra_spi_init()
Reviewed-on: https://chromium-review.googlesource.com/174639
(cherry picked from commit 88354b996459a702c36604f5f92c24e63df8de7e)

nyan: Set CrOS EC frame header parameters for SPI
Reviewed-on: https://chromium-review.googlesource.com/174710
(cherry picked from commit 29173ba5863eebb2864a8384435cde2f0d5ca233)

tegra124: Add Rx frame header support to SPI code
Reviewed-on: https://chromium-review.googlesource.com/174711
(cherry picked from commit 1d1630e770804649ef74d31db194d3bde9968832)

tegra124: add support for the Serial Output Resource (sor)
Reviewed-on: https://chromium-review.googlesource.com/174612
(cherry picked from commit 3eebd10afea4498380582e04560af89126911ed9)

nyan: tegra124: Enable I, D and L2 caches in romstage.
Reviewed-on: https://chromium-review.googlesource.com/173777
(cherry picked from commit 74512b7ecfbd50f01a25677307084699ee8c6007)

tegra and tegra124: Bring up graphics
Reviewed-on: https://chromium-review.googlesource.com/174613
(cherry picked from commit 7e944208a176cdac44a31e2a9961c8bd5dc4ece8)

nyan: Move the DMA memory region.
Reviewed-on: https://chromium-review.googlesource.com/174953
(cherry picked from commit c66e22859252eaebceb07a3118ac61f4cf6289eb)

tegra124: Increase CBFS cache buffer size
Reviewed-on: https://chromium-review.googlesource.com/174950
(cherry picked from commit 6dbb4e5f0d66c68df45ac73e3f223b856b715026)

tegra124: Add USB PLL, PHY and EHCI setup code
Reviewed-on: https://chromium-review.googlesource.com/174651
(cherry picked from commit ecd5c398ff6748a7d40089019471357b58d3a6ea)

tegra124: add in some undocument clock source and PLL registers
Reviewed-on: https://chromium-review.googlesource.com/174948
(cherry picked from commit 73fcc4981da6e4415b514eaafb42bc265ab0cd9a)

tegra124: small cleanups of the code
Reviewed-on: https://chromium-review.googlesource.com/174995
(cherry picked from commit 7256aba07e9567ef8d73f05e1f80c4d45fd57bda)

Squashed 34 commits for tegra124 / nyan support.

Change-Id: I050c7ad962e0d24550b0b33c9318e89c80d01f00
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6870
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)

1 files changed, 120 insertions, 0 deletions

diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c
new file mode 100644
index 0000000000..0a3434fb0d
--- /dev/null
+++ b/src/soc/nvidia/tegra/usb.c
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <delay.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <soc/clock.h>
+
+#include "usb.h"
+
+/* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */
+void usb_setup_utmip(struct usb_ctlr *usb)
+{
+	/* KHz formulas were guessed from U-Boot constants. Formats unclear. */
+	int khz = clock_get_osc_khz();
+
+	/* Stop UTMI+ crystal clock while we mess with its settings */
+	clrbits_le32(&usb->utmip.misc1, 1 << 30);	/* PHY_XTAL_CLKEN */
+	udelay(1);
+
+	/* Take stuff out of pwrdn and add some magic numbers from U-Boot */
+	write32(0x8 << 25 |		/* HS slew rate [10:4] */
+		0x3 << 22 |		/* HS driver output 'SETUP' [6:4] */
+		0 << 21 |		/* LS bias selection */
+		0 << 18 |		/* PDZI pwrdn */
+		0 << 16 |		/* PD2 pwrdn */
+		0 << 14 |		/* PD pwrdn */
+		1 << 13 |		/* (rst) HS receiver terminations */
+		0x1 << 10 |		/* (rst) LS falling slew rate */
+		0x1 << 8 |		/* (rst) LS rising slew rate */
+		0x4 << 0 |		/* HS driver output 'SETUP' [3:0] */
+		0, &usb->utmip.xcvr0);
+	write32(0x7 << 18 |		/* Termination range adjustment */
+		0 << 4 |		/* PDDR pwrdn */
+		0 << 2 |		/* PDCHRP pwrdn */
+		0 << 0 |		/* PDDISC pwrdn */
+		0, &usb->utmip.xcvr1);
+	write32(1 << 19 |		/* FS send initial J before sync(?) */
+		1 << 16 |		/* (rst) Allow stuff error on SoP */
+		1 << 9 |		/* (rst) Check disc only on EoP */
+		0, &usb->utmip.tx);
+	write32(0x2 << 30 |		/* (rst) Keep pattern on active */
+		1 << 28 |		/* (rst) Realign inertia on pkt */
+		0x1 << 24 |		/* (rst) edges-1 to move sampling */
+		0x3 << 21 |		/* (rst) squelch delay on EoP */
+		0x11 << 15 |		/* cycles until IDLE */
+		0x10 << 10 |		/* elastic input depth */
+		0, &usb->utmip.hsrx0);
+
+	/* U-Boot claims the USBD values for these are used across all UTMI+
+	 * PHYs. That sounds so horribly wrong that I'm not going to implement
+	 * it, but keep it in mind if we're ever not using the USBD port. */
+	write32(0x1 << 24 |		/* HS disconnect detect level [2] */
+		1 << 23 |		/* (rst) IDPD value */
+		1 << 22 |		/* (rst) IDPD select */
+		1 << 11 |		/* (rst) OTG pwrdn */
+		0 << 10 |		/* bias pwrdn */
+		0x1 << 2 |		/* HS disconnect detect level [1:0] */
+		0x2 << 0 |		/* HS squelch detect level */
+		0, &usb->utmip.bias0);
+
+	write32(khz / 2200 << 3 |	/* bias pwrdn cycles (20us?) */
+		1 << 2 |		/* (rst) VBUS wakeup pwrdn */
+		0 << 0 |		/* PDTRK pwrdn */
+		0, &usb->utmip.bias1);
+
+	write32(0xffff << 16 |		/* (rst) */
+		25 * khz / 10 << 0 |	/* TODO: what's this, really? */
+		0, &usb->utmip.debounce);
+
+	udelay(1);
+	setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */
+
+	write32(1 << 12 |		/* UTMI+ enable */
+		0 << 11 |		/* UTMI+ reset */
+		0, &usb->suspend_ctrl);
+}
+
+/*
+ * Tegra EHCI controllers need their usb_mode and lpm_ctrl registers initialized
+ * after every EHCI reset and before any other actions (such as Run/Stop bit)
+ * are taken. We reset the controller here, set those registers and rely on the
+ * fact that libpayload doesn't reset EHCI controllers on initialization for
+ * whatever weird reason. This is ugly, fragile, and I really don't like it, but
+ * making this work will require an ugly hack one way or another so we might as
+ * well take the path of least resistance for now.
+ */
+void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type)
+{
+	int timeout = 1000;
+
+	write32(1 << 1, &usb->ehci_usbcmd);	/* Host Controller Reset */
+	/* TODO: Resets are long, find way to parallelize... or just use XHCI */
+	while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1))
+		/* wait for HC to reset */;
+
+	if (!timeout) {
+		printk(BIOS_ERR, "ERROR: EHCI(%p) reset timeout", usb);
+		return;
+	}
+
+	write32(3 << 0, &usb->usb_mode);	/* Controller mode: HOST */
+	write32(type << 29, &usb->lpm_ctrl);	/* Parallel transceiver selct */
+}