tegra124/nyan: rougly stable code base

nyan: Clock setup.
Reviewed-on: https://chromium-review.googlesource.com/172106
(cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1)

tegra124: Call into the mainboard bootblock init if one exists.
Reviewed-on: https://chromium-review.googlesource.com/172581
(cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec)

nyan: Add a mainboard specific bootblock.
Reviewed-on: https://chromium-review.googlesource.com/172582
(cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69)

nyan: tegra124: Redestribute the clock code between the mainboard and soc.
Reviewed-on: https://chromium-review.googlesource.com/172583
(cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b)

nyan: Initialize the i2c pins and controllers.
Reviewed-on: https://chromium-review.googlesource.com/172584
(cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8)

nyan: Initialize the PMIC.
Reviewed-on: https://chromium-review.googlesource.com/172585
(cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a)

tegra124: add a chip.h and use it in NYAN
Reviewed-on: https://chromium-review.googlesource.com/172773
(cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f)

tegra: Reorder GPIO register accesses to avoid glitching
Reviewed-on: https://chromium-review.googlesource.com/172730
(cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5)

tegra: Turn GPIO wrappers into macros to make them easier to write
Reviewed-on: https://chromium-review.googlesource.com/172731
(cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c)

tegra: Change GPIO functions to allow variable arguments
Reviewed-on: https://chromium-review.googlesource.com/172916
(cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d)

tegra124: Implement starting up the main CPUs.
Reviewed-on: https://chromium-review.googlesource.com/172917
(cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3)

tegra: Simplify the I2C constants.
Reviewed-on: https://chromium-review.googlesource.com/172953
(cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76)

tegra124: Fix SPI base addresses
Reviewed-on: https://chromium-review.googlesource.com/173322
(cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357)

tegra124: Scrub the clock constants.
Reviewed-on: https://chromium-review.googlesource.com/172954
(cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4)

tegra124: add DMA support
Reviewed-on: https://chromium-review.googlesource.com/172951
(cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8)

tegra124: add basic SPI driver
Reviewed-on: https://chromium-review.googlesource.com/172952
(cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429)

tegra124: Add an assembly stub which is run first on the main CPUs.
Reviewed-on: https://chromium-review.googlesource.com/173541
(cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de)

nyan: tegra124: Set up dynamic cbmem.
Reviewed-on: https://chromium-review.googlesource.com/173542
(cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f)

tegra124: Add an soc.c which sets up the chip operations and memory resource.
Reviewed-on: https://chromium-review.googlesource.com/173543
(cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4)

tegra124: extend chip.h to include video settings
Reviewed-on: https://chromium-review.googlesource.com/173600
(cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29)

tegra124 and nyan: fill in the devicetree a bit more, add defines
Reviewed-on: https://chromium-review.googlesource.com/173684
(cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147)

tegra124: clean-ups for SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173599
(cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7)

tegra124: add a #define for DMA alignment size
Reviewed-on: https://chromium-review.googlesource.com/173638
(cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af)

tegra124: Add FIFO transmit functions to SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173639
(cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7)

tegra124: clean-ups for DMA driver
Reviewed-on: https://chromium-review.googlesource.com/173598
(cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0)

tegra124: early display and display code.
Reviewed-on: https://chromium-review.googlesource.com/173622
(cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558)

tegra124: Move transfer size handling to spi_xfer()
Reviewed-on: https://chromium-review.googlesource.com/173680
(cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621)

tegra124: strict error detection and reporting for SPI
Reviewed-on: https://chromium-review.googlesource.com/173681
(cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010)

tegra124: add thread-friendly delays to SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173648
(cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e)

Tegra124: Take the SPI1 controller out of reset and enable its clock.
Reviewed-on: https://chromium-review.googlesource.com/173787
(cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2)

tegra124: add two more clock setting values
Reviewed-on: https://chromium-review.googlesource.com/173772
(cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57)

nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC.
Reviewed-on: https://chromium-review.googlesource.com/173788
(cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8)

tegra124: Add some stub functions to the Tegra SPI driver.
Reviewed-on: https://chromium-review.googlesource.com/173789
(cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2)

tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS.
Reviewed-on: https://chromium-review.googlesource.com/173790
(cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084)

nyan: Implement the code which reads GPIOs for ChromeOS.
Reviewed-on: https://chromium-review.googlesource.com/173791
(cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3)

nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options.
Reviewed-on: https://chromium-review.googlesource.com/173792
(cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e)

Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks.
Reviewed-on: https://chromium-review.googlesource.com/173793
(cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88)

tegra124: fix clear_fifo_status() in SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173738
(cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f)

ARM: Include stdint.h in cpu.h.
Reviewed-on: https://chromium-review.googlesource.com/173774
(cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6)

tegra124: When setting up the main CPU, set its CPSR appropriately.
Reviewed-on: https://chromium-review.googlesource.com/173775
(cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead)

tegra124: fix wrong names in clk_rst.h
Reviewed-on: https://chromium-review.googlesource.com/173955
(cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d)

tegra124: Fix up the PLLX divider table.
Reviewed-on: https://chromium-review.googlesource.com/173778
(cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17)

tegra124: clock: Get rid of cpcon and dccon.
Reviewed-on: https://chromium-review.googlesource.com/173779
(cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7)

Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus.
Reviewed-on: https://chromium-review.googlesource.com/173953
(cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355)

armv7: expose dcache_line_bytes() in cache API
Reviewed-on: https://chromium-review.googlesource.com/173975
(cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12)

libpayload: expose dcache_line_bytes() in ARM cache API
Reviewed-on: https://chromium-review.googlesource.com/174099
(cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9)

armv4: add a stub for dcache_line_bytes()
Reviewed-on: https://chromium-review.googlesource.com/173976
(cherry picked from commit 924f61ea895b9268c716791466637009bbac6469)

tegra124: Base early UART on CLK_M to enable debugging of PLL init code
Reviewed-on: https://chromium-review.googlesource.com/174339
(cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa)

tegra124: Add additional PLLs and redesign the divisor table
Reviewed-on: https://chromium-review.googlesource.com/174380
(cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384)

Squashed 49 commits for tegra124/nyan that included a lot of churn on
different pieces.

Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6869
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

1 files changed, 68 insertions, 111 deletions

diff --git a/src/soc/nvidia/tegra/i2c.h b/src/soc/nvidia/tegra/i2c.h
index 630d890c38..997ec9c18f 100644
--- a/src/soc/nvidia/tegra/i2c.h
+++ b/src/soc/nvidia/tegra/i2c.h
@@ -24,133 +24,90 @@
 
 void i2c_init(unsigned bus);
 
-#define IOHEADER_BITFIELD(name, shift, mask) \
-	IOHEADER_##name##_SHIFT = shift, \
-	IOHEADER_##name##_MASK = \
-		mask << IOHEADER_##name##_SHIFT
-
-#define IOHEADER_BITFIELD_VAL(field, name, val) \
-	IOHEADER_##field##_##name = \
-		val << IOHEADER_##field##_SHIFT
-
 enum {
 	/* Word 0 */
-	IOHEADER_BITFIELD(WORD0_PROTHDRSZ, 28, 0x3),
-
-	IOHEADER_BITFIELD(WORD0_PKTID, 16, 0xff),
-
-	IOHEADER_BITFIELD(WORD0_CONTROLLER_ID, 12, 0xf),
-
-	IOHEADER_BITFIELD(WORD0_PROTOCOL, 4, 0xf),
-	IOHEADER_BITFIELD_VAL(WORD0_PROTOCOL, I2C, 1),
-
-	IOHEADER_BITFIELD(WORD0_PKTTYPE, 0, 0x7),
-	IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, REQUEST, 0),
-	IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, RESPONSE, 1),
-	IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, INTERRUPT, 2),
-	IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, STOP, 3),
+	IOHEADER_PROTHDRSZ_SHIFT = 28,
+	IOHEADER_PROTHDRSZ_MASK = 0x3 << IOHEADER_PROTHDRSZ_SHIFT,
+	IOHEADER_PKTID_SHIFT = 16,
+	IOHEADER_PKTID_MASK = 0xff << IOHEADER_PKTID_SHIFT,
+	IOHEADER_CONTROLLER_ID_SHIFT = 12,
+	IOHEADER_CONTROLLER_ID_MASK = 0xf << IOHEADER_CONTROLLER_ID_SHIFT,
+	IOHEADER_PROTOCOL_SHIFT = 4,
+	IOHEADER_PROTOCOL_MASK = 0xf << IOHEADER_PROTOCOL_SHIFT,
+	IOHEADER_PROTOCOL_I2C = 1 << IOHEADER_PROTOCOL_SHIFT,
+	IOHEADER_PKTTYPE_SHIFT = 0,
+	IOHEADER_PKTTYPE_MASK = 0x7 << IOHEADER_PKTTYPE_SHIFT,
+	IOHEADER_PKTTYPE_REQUEST = 0 << IOHEADER_PKTTYPE_SHIFT,
+	IOHEADER_PKTTYPE_RESPONSE = 1 << IOHEADER_PKTTYPE_SHIFT,
+	IOHEADER_PKTTYPE_INTERRUPT = 2 << IOHEADER_PKTTYPE_SHIFT,
+	IOHEADER_PKTTYPE_STOP = 3 << IOHEADER_PKTTYPE_SHIFT,
 
 	/* Word 1 */
-	IOHEADER_BITFIELD(WORD1_PAYLOADSIZE, 0, 0xfff)
+	IOHEADER_PAYLOADSIZE_SHIFT = 0,
+	IOHEADER_PAYLOADSIZE_MASK = 0xfff << IOHEADER_PAYLOADSIZE_SHIFT
 };
 
 enum {
-	IOHEADER_BITFIELD(I2C_REQ_RESP_PKT_FREQ_SHIFT, 25, 0x1),
-	IOHEADER_BITFIELD_VAL(I2C_REQ_RESP_PKT_FREQ_SHIFT, END, 0),
-	IOHEADER_BITFIELD_VAL(I2C_REQ_RESP_PKT_FREQ_SHIFT, EACH, 1),
-
-	IOHEADER_BITFIELD(I2C_REQ_RESP_PKT_ENABLE, 24, 0x1),
-
-	IOHEADER_BITFIELD(I2C_REQ_HS_MODE, 22, 0x1),
-
-	IOHEADER_BITFIELD(I2C_REQ_CONTINUE_ON_NACK, 21, 0x1),
-
-	IOHEADER_BITFIELD(I2C_REQ_SEND_START_BYTE, 20, 0x1),
-
-	IOHEADER_BITFIELD(I2C_REQ_READ_WRITE, 19, 0x1),
-	IOHEADER_BITFIELD_VAL(I2C_REQ_READ_WRITE, WRITE, 0),
-	IOHEADER_BITFIELD_VAL(I2C_REQ_READ_WRITE, READ, 1),
-
-	IOHEADER_BITFIELD(I2C_REQ_ADDRESS_MODE, 18, 0x1),
-	IOHEADER_BITFIELD_VAL(I2C_REQ_ADDRESS_MODE, 7BIT, 0),
-	IOHEADER_BITFIELD_VAL(I2C_REQ_ADDRESS_MODE, 10BIT, 1),
-
-	IOHEADER_BITFIELD(I2C_REQ_IE, 17, 0x1),
-
-	IOHEADER_BITFIELD(I2C_REQ_REPEAT_START_STOP, 16, 0x1),
-	IOHEADER_BITFIELD_VAL(I2C_REQ_REPEAT_START_STOP, STOP, 0),
-	IOHEADER_BITFIELD_VAL(I2C_REQ_REPEAT_START_STOP, START, 1),
-
-	IOHEADER_BITFIELD(I2C_REQ_CONTINUE_XFER, 15, 0x1),
-
-	IOHEADER_BITFIELD(I2C_REQ_HS_MASTER_ADDR, 12, 0x7),
-
-	IOHEADER_BITFIELD(I2C_REQ_SLAVE_ADDR, 0, 0x3ff)
+	IOHEADER_I2C_REQ_RESP_FREQ_MASK = 0x1 << 25,
+	IOHEADER_I2C_REQ_RESP_FREQ_END = 0 << 25,
+	IOHEADER_I2C_REQ_RESP_FREQ_EACH = 1 << 25,
+	IOHEADER_I2C_REQ_RESP_ENABLE = 0x1 << 24,
+	IOHEADER_I2C_REQ_HS_MODE = 0x1 << 22,
+	IOHEADER_I2C_REQ_CONTINUE_ON_NACK = 0x1 << 21,
+	IOHEADER_I2C_REQ_SEND_START_BYTE = 0x1 << 20,
+	IOHEADER_I2C_REQ_READ = 0x1 << 19,
+	IOHEADER_I2C_REQ_ADDR_MODE_MASK = 0x1 << 18,
+	IOHEADER_I2C_REQ_ADDR_MODE_7BIT = 0 << 18,
+	IOHEADER_I2C_REQ_ADDR_MODE_10BIT = 1 << 18,
+	IOHEADER_I2C_REQ_IE = 0x1 << 17,
+	IOHEADER_I2C_REQ_REPEAT_START = 0x1 << 16,
+	IOHEADER_I2C_REQ_STOP = 0x0 << 16,
+	IOHEADER_I2C_REQ_CONTINUE_XFER = 0x1 << 15,
+	IOHEADER_I2C_REQ_HS_MASTER_ADDR_SHIFT = 12,
+	IOHEADER_I2C_REQ_HS_MASTER_ADDR_MASK =
+		0x7 << IOHEADER_I2C_REQ_HS_MASTER_ADDR_SHIFT,
+	IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT = 0,
+	IOHEADER_I2C_REQ_SLAVE_ADDR_MASK =
+		0x3ff << IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT
 };
 
 enum {
-	TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT = 15,
-	TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_MASK =
-		0x1 << TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT,
-	TEGRA_I2C_CNFG_DEBOUNCE_CNT_SHIFT = 12,
-	TEGRA_I2C_CNFG_DEBOUNCE_CNT_MASK =
-		0x7 << TEGRA_I2C_CNFG_DEBOUNCE_CNT_SHIFT,
-	TEGRA_I2C_CNFG_NEW_MASTER_FSM_SHIFT = 11,
-	TEGRA_I2C_CNFG_NEW_MASTER_FSM_MASK =
-		0x1 << TEGRA_I2C_CNFG_NEW_MASTER_FSM_SHIFT,
-	TEGRA_I2C_CNFG_PACKET_MODE_EN_SHIFT = 10,
-	TEGRA_I2C_CNFG_PACKET_MODE_EN_MASK =
-		0x1 << TEGRA_I2C_CNFG_PACKET_MODE_EN_SHIFT,
-	TEGRA_I2C_CNFG_SEND_SHIFT = 9,
-	TEGRA_I2C_CNFG_SEND_MASK = 0x1 << TEGRA_I2C_CNFG_SEND_SHIFT,
-	TEGRA_I2C_CNFG_NOACK_SHIFT = 8,
-	TEGRA_I2C_CNFG_NOACK_MASK = 0x1 << TEGRA_I2C_CNFG_NOACK_SHIFT,
-	TEGRA_I2C_CNFG_CMD2_SHIFT = 7,
-	TEGRA_I2C_CNFG_CMD2_MASK = 0x1 << TEGRA_I2C_CNFG_CMD2_SHIFT,
-	TEGRA_I2C_CNFG_CMD1_SHIFT = 6,
-	TEGRA_I2C_CNFG_CMD1_MASK = 0x1 << TEGRA_I2C_CNFG_CMD1_SHIFT,
-	TEGRA_I2C_CNFG_START_SHIFT = 5,
-	TEGRA_I2C_CNFG_START_MASK = 0x1 << TEGRA_I2C_CNFG_START_SHIFT,
-	TEGRA_I2C_CNFG_SLV2_SHIFT = 4,
-	TEGRA_I2C_CNFG_SLV2_MASK = 0x1 << TEGRA_I2C_CNFG_SLV2_SHIFT,
-	TEGRA_I2C_CNFG_LENGTH_SHIFT = 1,
-	TEGRA_I2C_CNFG_LENGTH_MASK = 0x7 << TEGRA_I2C_CNFG_LENGTH_SHIFT,
-	TEGRA_I2C_CNFG_A_MOD_SHIFT = 0,
-	TEGRA_I2C_CNFG_A_MOD_MASK = 0x1 << TEGRA_I2C_CNFG_A_MOD_SHIFT
+	I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT = 0x1 << 15,
+	I2C_CNFG_DEBOUNCE_CNT_SHIFT = 12,
+	I2C_CNFG_DEBOUNCE_CNT_MASK = 0x7 << I2C_CNFG_DEBOUNCE_CNT_SHIFT,
+	I2C_CNFG_NEW_MASTER_FSM = 0x1 << 11,
+	I2C_CNFG_PACKET_MODE_EN = 0x1 << 10,
+	I2C_CNFG_SEND = 0x1 << 9,
+	I2C_CNFG_NOACK = 0x1 << 8,
+	I2C_CNFG_CMD2 = 0x1 << 7,
+	I2C_CNFG_CMD1 = 0x1 << 6,
+	I2C_CNFG_START = 0x1 << 5,
+	I2C_CNFG_SLV2_SHIFT = 4,
+	I2C_CNFG_SLV2_MASK = 0x1 << I2C_CNFG_SLV2_SHIFT,
+	I2C_CNFG_LENGTH_SHIFT = 1,
+	I2C_CNFG_LENGTH_MASK = 0x7 << I2C_CNFG_LENGTH_SHIFT,
+	I2C_CNFG_A_MOD = 0x1 << 0,
 };
 
 enum {
-	TEGRA_I2C_PKT_STATUS_COMPLETE_SHIFT = 24,
-	TEGRA_I2C_PKT_STATUS_COMPLETE_MASK =
-		0x1 << TEGRA_I2C_PKT_STATUS_COMPLETE_SHIFT,
-	TEGRA_I2C_PKT_STATUS_PKT_ID_SHIFT = 16,
-	TEGRA_I2C_PKT_STATUS_PKT_ID_MASK =
-		0xff << TEGRA_I2C_PKT_STATUS_PKT_ID_SHIFT,
-	TEGRA_I2C_PKT_STATUS_BYTENUM_SHIFT = 4,
-	TEGRA_I2C_PKT_STATUS_BYTENUM_MASK =
-		0xfff << TEGRA_I2C_PKT_STATUS_BYTENUM_SHIFT,
-	TEGRA_I2C_PKT_STATUS_NOACK_ADDR_SHIFT = 3,
-	TEGRA_I2C_PKT_STATUS_NOACK_ADDR_MASK =
-		0x1 << TEGRA_I2C_PKT_STATUS_NOACK_ADDR_SHIFT,
-	TEGRA_I2C_PKT_STATUS_NOACK_DATA_SHIFT = 2,
-	TEGRA_I2C_PKT_STATUS_NOACK_DATA_MASK =
-		0x1 << TEGRA_I2C_PKT_STATUS_NOACK_DATA_SHIFT,
-	TEGRA_I2C_PKT_STATUS_ARB_LOST_SHIFT = 1,
-	TEGRA_I2C_PKT_STATUS_ARB_LOST_MASK =
-		0x1 << TEGRA_I2C_PKT_STATUS_ARB_LOST_SHIFT,
-	TEGRA_I2C_PKT_STATUS_BUSY_SHIFT = 0,
-	TEGRA_I2C_PKT_STATUS_BUSY_MASK =
-		0x1 << TEGRA_I2C_PKT_STATUS_BUSY_SHIFT,
+	I2C_PKT_STATUS_COMPLETE = 0x1 << 24,
+	I2C_PKT_STATUS_PKT_ID_SHIFT = 16,
+	I2C_PKT_STATUS_PKT_ID_MASK = 0xff << I2C_PKT_STATUS_PKT_ID_SHIFT,
+	I2C_PKT_STATUS_BYTENUM_SHIFT = 4,
+	I2C_PKT_STATUS_BYTENUM_MASK = 0xfff << I2C_PKT_STATUS_BYTENUM_SHIFT,
+	I2C_PKT_STATUS_NOACK_ADDR = 0x1 << 3,
+	I2C_PKT_STATUS_NOACK_DATA = 0x1 << 2,
+	I2C_PKT_STATUS_ARB_LOST = 0x1 << 1,
+	I2C_PKT_STATUS_BUSY = 0x1 << 0
 };
 
 enum {
-	TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT = 4,
-	TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK =
-		0xf << TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT,
-
-	TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT = 0,
-	TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK =
-		0xf << TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT
+	I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT = 4,
+	I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK =
+		0xf << I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT,
+	I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT = 0,
+	I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK =
+		0xf << I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT
 };
 
 extern void * const tegra_i2c_bases[];