soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz

Mediatek SoCs start operating at eMMC clock around 3MHz right after
power-on due to wrong src_hz value. In JEDEC spec, eMMC clock needs
under 400kHz.

When we need to set a clock output frequency, we actually set a
frequency division value. Originally, we set the source clock
frequency to 50MHz, the target frequency to 400KHz, and get the
division value 128. However, the actual source clock frequency is
400MHz, so the final actual output is 400MHz/128=3.125MHz.

So we correct source clock frequency to 400MHz for eMMC output
clock of 400KHz.

BUG=b:356578805
TEST=test boot ok; measure eMMC clock ok; no boot time impact

Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com>
Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84298
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/src/soc/mediatek/common/msdc.c b/src/soc/mediatek/common/msdc.c
index df59b0ee37..fbab8d8bfb 100644
--- a/src/soc/mediatek/common/msdc.c
+++ b/src/soc/mediatek/common/msdc.c
@@ -429,7 +429,7 @@ static void msdc_controller_init(struct msdc_ctrlr *host, void *base, void *top_
 	memset(host, 0, sizeof(*host));
 	host->base = base;
 	host->top_base = top_base;
-	host->src_hz = 50 * 1000 * 1000;
+	host->src_hz = 400 * 1000 * 1000;
 
 	add_msdc(host);
 }