soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING

HW TX tracking works by writing a pattern to the designated DRAM buffer
and then reading it back automatically to calculate the appropriate TX
time delay. To avoid writing the pattern to system-used memory, we need
to permanently reserve last 64KB memory on each rank for the HW TX
tracking feature.

BUG=b:317009620
TEST=Reserve memory ok
Firmware shows the following log with 12GB DDR board:
00000001ffff0000-00000001ffffffff: RESERVED
000000037fff0000-000000037fffffff: RESERVED

Change-Id: I042a74c7fbdc0d3dc19dd6bfd2bf021fe1c2b5fc
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85124
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>

4 files changed, 52 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index c0b491452e..82a907644e 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -30,6 +30,7 @@ romstage-y += ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 
 ramstage-y += ../common/dpm_v2.c
+ramstage-y += dramc_info.c
 ramstage-y += ../common/early_init.c
 ramstage-y += ../common/emi.c
 ramstage-y += l2c_ops.c
diff --git a/src/soc/mediatek/mt8196/dramc_info.c b/src/soc/mediatek/mt8196/dramc_info.c
new file mode 100644
index 0000000000..d64796370f
--- /dev/null
+++ b/src/soc/mediatek/mt8196/dramc_info.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <bootmem.h>
+#include <cbmem.h>
+#include <commonlib/bsd/mem_chip_info.h>
+#include <soc/dramc_info.h>
+#include <soc/dramc_soc.h>
+#include <symbols.h>
+
+void reserve_buffer_for_dramc(void)
+{
+	const struct mem_chip_info *mc = cbmem_find(CBMEM_ID_MEM_CHIP_INFO);
+	int i;
+	const uint32_t reserved_size = 64 * KiB;
+	uint64_t cbmem_top_addr = cbmem_top();
+	uint64_t reserved_addr;
+	uint64_t rank_size_sum = 0;
+	uint64_t rank_size[RANK_MAX] = {0};
+
+	assert(mc);
+
+	for (i = 0; i < mc->num_entries; i++) {
+		const struct mem_chip_entry *e = &mc->entries[i];
+		assert(e->rank < RANK_MAX);
+		rank_size[e->rank] += mem_chip_info_entry_density_bytes(e);
+	}
+
+	for (i = 0; i < RANK_MAX; i++) {
+		if (rank_size[i] == 0)
+			continue;
+		rank_size_sum += rank_size[i];
+		assert(rank_size_sum >= reserved_size);
+
+		reserved_addr = (uint64_t)_dram + rank_size_sum - reserved_size;
+		/* Reserved range must not overlap with CBMEM. */
+		assert(reserved_addr >= cbmem_top_addr);
+		bootmem_add_range(reserved_addr, reserved_size, BM_MEM_RESERVED);
+	}
+}
diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_info.h b/src/soc/mediatek/mt8196/include/soc/dramc_info.h
new file mode 100644
index 0000000000..ccc7ff9b97
--- /dev/null
+++ b/src/soc/mediatek/mt8196/include/soc/dramc_info.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8196_DRAMC_INFO_H__
+#define __SOC_MEDIATEK_MT8196_DRAMC_INFO_H__
+
+void reserve_buffer_for_dramc(void);
+
+#endif	/* __SOC_MEDIATEK_MT8196_DRAMC_INFO_H__ */
diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c
index d3aeb5a72c..8aca5d6e5d 100644
--- a/src/soc/mediatek/mt8196/soc.c
+++ b/src/soc/mediatek/mt8196/soc.c
@@ -2,6 +2,7 @@
 
 #include <device/device.h>
 #include <device/pci.h>
+#include <soc/dramc_info.h>
 #include <soc/emi.h>
 #include <soc/mmu_operations.h>
 #include <soc/pcie.h>
@@ -13,6 +14,8 @@ void bootmem_platform_add_ranges(void)
 	if (CONFIG(ARM64_BL31_OPTEE_WITH_SMC))
 		bootmem_add_range((uint64_t)_resv_mem_optee,
 				  REGION_SIZE(resv_mem_optee), BM_MEM_RESERVED);
+
+	reserve_buffer_for_dramc();
 }
 
 static void soc_read_resources(struct device *dev)