diff options
| author | Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> | 2024-08-16 10:33:17 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-24 13:00:04 +0000 |
| commit | 6c8974b5c746b37e31365d511c7499c3e5887cb8 (patch) | |
| tree | 5bcde54b9acd327592f9438fcb8f8052d922f10e /src/soc/mediatek | |
| parent | abf34584dbfecdd74db36dd24f6008d1051a96a9 (diff) | |
soc/mediatek/mt8196: Enable MMU operation for L2C SRAM and DMA
- Turn off L2C SRAM and reconfigure as L2 cache:
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
- Configure DMA buffer in DRAM:
Set DRAM DMA to be non-cacheable to load blob correctly.
TEST=build pass, register(disable_l2c) read ok
BUG=b:317009620
Change-Id: I6a3cb63d3418f085f5d8d08b282dd59ea431c294
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83925
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/mt8196/Makefile.mk | 4 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8196/l2c_ops.c | 45 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8196/soc.c | 2 |
3 files changed, 51 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 96aea39986..44fa59e927 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -13,8 +13,12 @@ bootblock-y += ../common/mmu_operations.c romstage-y += ../common/cbmem.c romstage-y += emi.c +romstage-y += l2c_ops.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-y += emi.c +ramstage-y += l2c_ops.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-y += soc.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8196/include diff --git a/src/soc/mediatek/mt8196/l2c_ops.c b/src/soc/mediatek/mt8196/l2c_ops.c new file mode 100644 index 0000000000..b51c49cc15 --- /dev/null +++ b/src/soc/mediatek/mt8196/l2c_ops.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 9 + */ + +#include <device/mmio.h> +#include <soc/mmu_operations.h> + +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_FULLNHALF, 0) +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 1) +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 2) + +#define MP0_CLUSTER_CFG0 0x0C000060 +#define CLUST_DIS_VAL 0x3 +#define CLUST_DIS_SHIFT 0x4 + +void mtk_soc_disable_l2c_sram(void) +{ + unsigned long v; + + uint32_t *mp0_cluster_cfg0 = (void *)(MP0_CLUSTER_CFG0); + + SET32_BITFIELDS(mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_EN, 0); + dsb(); + + __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v)); + v |= (CLUST_DIS_VAL << CLUST_DIS_SHIFT); + __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v)); + dsb(); + + do { + __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v)); + } while (((v >> CLUST_DIS_SHIFT) & CLUST_DIS_VAL) != CLUST_DIS_VAL); + + SET32_BITFIELDS(mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); + + SET32_BITFIELDS(mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_FULLNHALF, 0); + + dsb(); +} diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c index b77735ceed..b62c055426 100644 --- a/src/soc/mediatek/mt8196/soc.c +++ b/src/soc/mediatek/mt8196/soc.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <soc/emi.h> +#include <soc/mmu_operations.h> #include <symbols.h> static void soc_read_resources(struct device *dev) @@ -11,6 +12,7 @@ static void soc_read_resources(struct device *dev) static void soc_init(struct device *dev) { + mtk_mmu_disable_l2c_sram(); } static struct device_operations soc_ops = { |