diff options
| author | henryc.chen <henryc.chen@mediatek.com> | 2016-04-25 15:53:29 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-05-09 08:36:57 +0200 |
| commit | 53e78539de11fa4f52348fa711d723742802a479 (patch) | |
| tree | d0a39ba5bca2351d5385f8cceb06fa5385e27de9 /src/soc/mediatek | |
| parent | b7041a7ee28e3f2c4442649fef0f14c88b38d5b3 (diff) | |
soc/mediatek/mt8173: mt6391: vcore sleep voltage should be 0.7V
Vcore voltage should be 0.7V during system suspend. Because data sheet of mt6391
was not correct, need to config to 0x0 instead of 0x1.
QI_VCORE_VSLEEP
00: 0.7V
01: 0.6V
10: 0.65V
11: 0.75V
BUG=chrome-os-partner:52719
TEST=powerd_dbus_suspend
Change-Id: Ie504ebfb7cafae85bbba7919fce1578bbfbfafb7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf15f5b63fac8968216772a8b37d2fe122414e24
Original-Change-Id: Ide53eca328c28007e2181497c888724c8a91ae93
Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/340540
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14696
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/mt8173/mt6391.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index f88fb8efca..ec7fabc554 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -193,7 +193,7 @@ static void mt6391_init_setting(void) /* [12:0]: BUCK_RSV; for OC protection */ mt6391_write(PMIC_RG_BUCK_CON3, 0x600, 0x0FFF, 0); /* [11:10]: QI_VCORE_VSLEEP; sleep mode only (0.7V) */ - mt6391_write(PMIC_RG_BUCK_CON8, 0x1, 0x3, 10); + mt6391_write(PMIC_RG_BUCK_CON8, 0x0, 0x3, 10); /* [7:6]: QI_VSRMCA7_VSLEEP; sleep mode only (0.85V) */ mt6391_write(PMIC_RG_BUCK_CON8, 0x0, 0x3, 6); /* [5:4]: QI_VSRMCA15_VSLEEP; sleep mode only (0.7V) */ |