soc/mediatek/mt8195: Add PLL and clock init support

Add PLL and clock init code.
Add frequency meter and API for raising little CPU/CCI frequency.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I8ded0236d10826687f080bd5a213feb55d4bae03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52667
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 1876 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index 0da0cef70b..b3e12e95f2 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y)
 bootblock-y += bootblock.c
 bootblock-y += ../common/gpio.c gpio.c
 bootblock-y += ../common/mmu_operations.c
+bootblock-y += ../common/pll.c pll.c
 bootblock-$(CONFIG_SPI_FLASH) += spi.c
 bootblock-y += ../common/timer.c timer.c
 bootblock-y += ../common/uart.c
@@ -17,6 +18,7 @@ verstage-y += ../common/wdt.c
 romstage-y += ../common/cbmem.c
 romstage-y += emi.c
 romstage-y += ../common/gpio.c gpio.c
+romstage-y += ../common/pll.c pll.c
 romstage-$(CONFIG_SPI_FLASH) += spi.c
 romstage-y += ../common/timer.c timer.c
 romstage-y += ../common/uart.c
diff --git a/src/soc/mediatek/mt8195/bootblock.c b/src/soc/mediatek/mt8195/bootblock.c
index 770c6031da..8dffe5671b 100644
--- a/src/soc/mediatek/mt8195/bootblock.c
+++ b/src/soc/mediatek/mt8195/bootblock.c
@@ -2,10 +2,12 @@
 
 #include <bootblock_common.h>
 #include <soc/mmu_operations.h>
+#include <soc/pll.h>
 #include <soc/wdt.h>
 
 void bootblock_soc_init(void)
 {
 	mtk_mmu_init();
 	mtk_wdt_init();
+	mt_pll_init();
 }
diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h
index 417e2bd2c2..85d0fad1e9 100644
--- a/src/soc/mediatek/mt8195/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h
@@ -23,6 +23,7 @@ enum {
 	EINT_BASE		= IO_PHYS + 0x0000B000,
 	APMIXED_BASE		= IO_PHYS + 0x0000C000,
 	SYSTIMER_BASE		= IO_PHYS + 0x00017000,
+	INFRACFG_AO_BCRM_BASE	= IO_PHYS + 0x00022000,
 	PMIF_SPI_BASE	 	= IO_PHYS + 0x00024000,
 	PMICSPI_MST_BASE	= IO_PHYS + 0x00025000,
 	PMIF_SPMI_BASE		= IO_PHYS + 0x00027000,
@@ -48,6 +49,7 @@ enum {
 	DPM_CFG_BASE2		= IO_PHYS + 0x00A40000,
 	AUXADC_BASE		= IO_PHYS + 0x01001000,
 	UART0_BASE		= IO_PHYS + 0x01001100,
+	PERICFG_AO_BASE		= IO_PHYS + 0x01003000,
 	SPI0_BASE		= IO_PHYS + 0x0100A000,
 	SPI1_BASE		= IO_PHYS + 0x01010000,
 	SPI2_BASE		= IO_PHYS + 0x01012000,
diff --git a/src/soc/mediatek/mt8195/include/soc/mcucfg.h b/src/soc/mediatek/mt8195/include/soc/mcucfg.h
new file mode 100644
index 0000000000..bb39096636
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/mcucfg.h
@@ -0,0 +1,969 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_MCUCFG_H
+#define SOC_MEDIATEK_MT8195_MCUCFG_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8195_mcucfg_regs {
+	u32 rsv_0000[2];
+	u32 mbista_mcsi_sf1_con;
+	u32 mbista_mcsi_sf1_result;
+	u32 mbista_mcsi_sf2_con;
+	u32 mbista_mcsi_sf2_result;
+	u32 mbista_etb_con;
+	u32 mbista_etb_result;
+	u32 mbista_rstb;
+	u32 mbista_all_result;
+	u32 rsv_0028[2];
+	u32 mbist_trigger_mux_ctl;
+	u32 rsv_0034[3];
+	u32 dfd_ctrl;
+	u32 dfd_cnt_l;
+	u32 dfd_cnt_h;
+	u32 rsv_004c[5];
+	u32 mp_top_dbg_mon_sel;
+	u32 mp_top_dbg_mon;
+	u32 mp0_dbg_mon_sel;
+	u32 mp0_dbg_mon;
+	u32 rsv_0070[28];
+	u32 mp0_ptp_sensor_sel;
+	u32 emi_addr_wrap_cfg;
+	u32 emi_addr_wrap_state;
+	u32 rsv_00ec[3];
+	u32 armpll_jit_clk_out_sel;
+	u32 rsv_00fc;
+	u32 cci_tra_cfg0;
+	u32 rsv_0104[4];
+	u32 cci_tra_cfg5;
+	u32 cci_tra_cfg6;
+	u32 cci_tra_cfg7;
+	u32 cci_tra_cfg8;
+	u32 cci_tra_cfg9;
+	u32 cci_tra_cfg10;
+	u32 cci_tra_cfg11;
+	u32 cci_tra_cfg12;
+	u32 rsv_0134[51];
+	u32 cci_m0_tra;
+	u32 cci_m1_tra;
+	u32 cci_m2_tra;
+	u32 rsv_020c[5];
+	u32 cci_s1_tra;
+	u32 cci_s2_tra;
+	u32 cci_s3_tra;
+	u32 cci_s4_tra;
+	u32 rsv_0230[4];
+	u32 cci_m0_tra_latch;
+	u32 cci_m1_tra_latch;
+	u32 cci_m2_tra_latch;
+	u32 rsv_024c[5];
+	u32 cci_s1_tra_latch;
+	u32 cci_s2_tra_latch;
+	u32 cci_s3_tra_latch;
+	u32 cci_s4_tra_latch;
+	u32 rsv_0270[20];
+	u32 cci_m0_if;
+	u32 cci_m1_if;
+	u32 cci_m2_if;
+	u32 rsv_02cc[5];
+	u32 cci_s1_if;
+	u32 cci_s2_if;
+	u32 cci_s3_if;
+	u32 cci_s4_if;
+	u32 rsv_02f0[12];
+	u32 cci_m0_if_latch;
+	u32 cci_m1_if_latch;
+	u32 cci_m2_if_latch;
+	u32 rsv_032c[5];
+	u32 cci_s1_if_latch;
+	u32 cci_s2_if_latch;
+	u32 cci_s3_if_latch;
+	u32 cci_s4_if_latch;
+	u32 rsv_0350[44];
+	u32 l3c_share_status0;
+	u32 l3c_share_status1;
+	u32 l3c_share_status2;
+	u32 rsv_040c;
+	u32 mp0_cpu0_dc_age;
+	u32 mp0_cpu1_dc_age;
+	u32 mp0_cpu2_dc_age;
+	u32 mp0_cpu3_dc_age;
+	u32 mp0_cpu4_dc_age;
+	u32 mp0_cpu5_dc_age;
+	u32 mp0_cpu6_dc_age;
+	u32 mp0_cpu7_dc_age;
+	u32 rsv_0430[52];
+	u32 mp0_cpu0_nonwfx_ctrl;
+	u32 mp0_cpu0_nonwfx_cnt;
+	u32 mp0_cpu1_nonwfx_ctrl;
+	u32 mp0_cpu1_nonwfx_cnt;
+	u32 mp0_cpu2_nonwfx_ctrl;
+	u32 mp0_cpu2_nonwfx_cnt;
+	u32 mp0_cpu3_nonwfx_ctrl;
+	u32 mp0_cpu3_nonwfx_cnt;
+	u32 mp0_cpu4_nonwfx_ctrl;
+	u32 mp0_cpu4_nonwfx_cnt;
+	u32 mp0_cpu5_nonwfx_ctrl;
+	u32 mp0_cpu5_nonwfx_cnt;
+	u32 mp0_cpu6_nonwfx_ctrl;
+	u32 mp0_cpu6_nonwfx_cnt;
+	u32 mp0_cpu7_nonwfx_ctrl;
+	u32 mp0_cpu7_nonwfx_cnt;
+	u32 rsv_0540[48];
+	u32 mp0_ses_apb_trig;
+	u32 mp0_ses_clk_en;
+	u32 rsv_0608[2];
+	u32 wfx_ret_met_dbc_sel;
+	u32 rsv_0614[3];
+	u32 adb_bist_cfg1;
+	u32 adb_bist_cfg2_md;
+	u32 adb_bist_cfg3_go;
+	u32 adb_bist_done;
+	u32 adb_bist_pass;
+	u32 adb_bist_done1;
+	u32 rsv_0638;
+	u32 adb_bist_pass1;
+	u32 rsv_0640[48];
+	u32 axi2acp_cfg_ctrl;
+	u32 axi2acp_cfg_mask_id;
+	u32 rsv_0708[2];
+	u32 axi2acp_ar_def_set;
+	u32 rsv_0714;
+	u32 axi2acp_aw_def_set;
+	u32 rsv_071c;
+	u32 axi2acp_err_addr0;
+	u32 axi2acp_err_addr1;
+	u32 axi2acp_err_st;
+	u32 axi2acp_err_id;
+	u32 axi2acp_err_irq;
+	u32 axi2acp_err_dbgout;
+	u32 rsv_0738[50];
+	u32 mst_ccim0_inject_fault;
+	u32 mst_ccim0_rec_par;
+	u32 mst_ccim0_log_rid;
+	u32 rsv_080c;
+	u32 mst_ccim0_log_rd0;
+	u32 mst_ccim0_log_rd1;
+	u32 mst_ccim0_log_rd2;
+	u32 mst_ccim0_log_rd3;
+	u32 mst_ccim1_inject_fault;
+	u32 mst_ccim1_rec_par;
+	u32 mst_ccim1_log_rid;
+	u32 rsv_082c;
+	u32 mst_ccim1_log_rd0;
+	u32 mst_ccim1_log_rd1;
+	u32 mst_ccim1_log_rd2;
+	u32 mst_ccim1_log_rd3;
+	u32 mst_intaxi_inject_fault;
+	u32 mst_intaxi_rec_par;
+	u32 mst_intaxi_log_rid;
+	u32 rsv_084c;
+	u32 mst_intaxi_log_rd0;
+	u32 mst_intaxi_log_rd1;
+	u32 rsv_0858[2];
+	u32 slv_1to2_inject_fault;
+	u32 slv_1to2_rec_par;
+	u32 slv_1to2_log_awid;
+	u32 slv_1to2_log_arid;
+	u32 slv_1to2_log_awa0;
+	u32 slv_1to2_log_awa1;
+	u32 slv_1to2_log_ara0;
+	u32 slv_1to2_log_ara1;
+	u32 slv_1to2_log_wid;
+	u32 rsv_0884[3];
+	u32 slv_1to2_log_wd0;
+	u32 slv_1to2_log_wd1;
+	u32 slv_1to2_log_wd2;
+	u32 slv_1to2_log_wd3;
+	u32 slv_l3c_inject_fault;
+	u32 slv_l3c_rec_par;
+	u32 slv_l3c_log_awid;
+	u32 slv_l3c_log_arid;
+	u32 slv_l3c_log_awa0;
+	u32 slv_l3c_log_awa1;
+	u32 slv_l3c_log_ara0;
+	u32 slv_l3c_log_ara1;
+	u32 slv_l3c_log_wid;
+	u32 rsv_08c4;
+	u32 slv_l3c_log_wd0;
+	u32 slv_l3c_log_wd1;
+	u32 slv_gic_inject_fault;
+	u32 slv_gic_rec_par;
+	u32 slv_gic_log_awid;
+	u32 slv_gic_log_arid;
+	u32 slv_gic_log_awa0;
+	u32 slv_gic_log_awa1;
+	u32 slv_gic_log_ara0;
+	u32 slv_gic_log_ara1;
+	u32 slv_gic_log_wid;
+	u32 rsv_08f4;
+	u32 slv_gic_log_wd0;
+	u32 slv_gic_log_wd1;
+	u32 rsv_0900[64];
+	u32 ildo_vin_big0;
+	u32 ildo_out_big0;
+	u32 ildo_ovstck_big0;
+	u32 ildo_vo2hck_big0;
+	u32 ildo_mhstck_big0;
+	u32 ildo_mlstck_big0;
+	u32 ilod_uvwin_big0;
+	u32 ilod_ovwin_big0;
+	u32 ildo_pd_cfg_big0;
+	u32 rsv_0a24[3];
+	u32 ildo_vin_big1;
+	u32 ildo_out_big1;
+	u32 ildo_ovstck_big1;
+	u32 ildo_vo2hck_big1;
+	u32 ildo_mhstck_big1;
+	u32 ildo_mlstck_big1;
+	u32 ilod_uvwin_big1;
+	u32 ilod_ovwin_big1;
+	u32 ildo_pd_cfg_big1;
+	u32 rsv_0a54[3];
+	u32 ildo_vin_big2;
+	u32 ildo_out_big2;
+	u32 ildo_ovstck_big2;
+	u32 ildo_vo2hck_big2;
+	u32 ildo_mhstck_big2;
+	u32 ildo_mlstck_big2;
+	u32 ilod_uvwin_big2;
+	u32 ilod_ovwin_big2;
+	u32 ildo_pd_cfg_big2;
+	u32 rsv_0a84[3];
+	u32 ildo_vin_big3;
+	u32 ildo_out_big3;
+	u32 ildo_ovstck_big3;
+	u32 ildo_vo2hck_big3;
+	u32 ildo_mhstck_big3;
+	u32 ildo_mlstck_big3;
+	u32 ilod_uvwin_big3;
+	u32 ilod_ovwin_big3;
+	u32 ildo_pd_cfg_big3;
+	u32 rsv_0ab4[1495];
+	u32 l3c_share_cfg0;
+	u32 l3c_share_cfg1;
+	u32 l3c_share_cfg2;
+	u32 rsv_221c;
+	u32 udi_cfg0;
+	u32 udi_cfg1;
+	u32 rsv_2228[2];
+	u32 mcusys_core_status;
+	u32 rsv_2234;
+	u32 cfg_sys_valid;
+	u32 cfg_sysbase_addr_0;
+	u32 cfg_sysbase_addr_1;
+	u32 cfg_sysbase_addr_2;
+	u32 cfg_sysbase_addr_3;
+	u32 cfg_sysbase_addr_4;
+	u32 rsv_2250[4];
+	u32 mcusys_base;
+	u32 l3c_sram_base;
+	u32 gic_periph_base;
+	u32 cci_periph_base;
+	u32 cci_periph_infra_base;
+	u32 dfd_sram_base;
+	u32 l3c_mm_sram_base;
+	u32 ext_l3c_sram_base;
+	u32 ext_gic_periph_base;
+	u32 mcusys_qos_shaper_degree;
+	u32 mcusys_qos_shaper_others;
+	u32 mcusys_qos_age_set_enable;
+	u32 sspm_cpueb_turbo_pll_ctl;
+	u32 cpu_eb_apb_base;
+	u32 cpu_eb_tcm_btb_delsel;
+	u32 cpu_eb_mem_misc;
+	u32 cpu_plldiv_cfg0;
+	u32 cpu_plldiv_cfg1;
+	u32 rsv_22a8[14];
+	u32 bus_plldiv_cfg;
+	u32 rsv_22e4[3];
+	u32 plldiv_ctl0;
+	u32 cpuplldiv_unictl;
+	u32 rsv_22f8[2];
+	u32 mcsi_ram_delsel0;
+	u32 mcsi_ram_delsel1;
+	u32 rsv_2308[7];
+	u32 mbist_delsel_fuse_dis;
+	u32 mbist_delsel_magic_key;
+	u32 rsv_232c[21];
+	u32 etb_cfg0;
+	u32 rsv_2384[3];
+	u32 bus_parity_gen_en;
+	u32 bus_parity_clr;
+	u32 bus_parity_chk_en;
+	u32 bus_parity_fail;
+	u32 dsu2biu_addr_remap_cfg;
+	u32 dsu2biu_addr_remap_sta;
+	u32 rsv_23a8[2];
+	u32 dsu2biu_addr_remap_0_cfg0;
+	u32 dsu2biu_addr_remap_0_cfg1;
+	u32 dsu2biu_addr_remap_0_cfg2;
+	u32 rsv_23bc;
+	u32 dsu2biu_addr_remap_1_cfg0;
+	u32 dsu2biu_addr_remap_1_cfg1;
+	u32 dsu2biu_addr_remap_1_cfg2;
+	u32 rsv_23cc;
+	u32 dsu2biu_addr_remap_magic;
+	u32 rsv_23d4[11];
+	u32 cci_rgu;
+	u32 rsv_2404[3];
+	u32 mcsi_cfg0;
+	u32 mcsi_cfg1;
+	u32 mcsi_cfg2;
+	u32 mcsi_cfg3;
+	u32 mcsi_cfg4;
+	u32 rsv_2424[7];
+	u32 mcsic_dcm0;
+	u32 mcsic_dcm1;
+	u32 rsv_2448[18];
+	u32 apmcu2emi_early_cke_ctl0;
+	u32 apmcu2emi_early_cke_ctl1;
+	u32 apmcu2emi_early_ebg_ctl0;
+	u32 apmcu2emi_early_ebg_ctl1;
+	u32 apmcu2emi_early_ebg_ctl2;
+	u32 apmcu2emi_early_ebg_ctl3;
+	u32 apmcu2emi_early_ebg_ctl4;
+	u32 apmcu2emi_early_ebg_ctl5;
+	u32 apmcu2emi_early_ebg_enable01;
+	u32 apmcu2emi_early_ebg_enable23;
+	u32 emi_hash_violation;
+	u32 emi_interleave_update_mask;
+	u32 rsv_24c0[16];
+	u32 mp_adb_dcm_cfg0;
+	u32 rsv_2504;
+	u32 mp_adb_dcm_cfg2;
+	u32 rsv_250c;
+	u32 mp_adb_dcm_cfg4;
+	u32 rsv_2514;
+	u32 mp_misc_dcm_cfg0;
+	u32 rsv_251c[9];
+	u32 etb_ck_ctl;
+	u32 rsv_2544[15];
+	u32 dcc_cpu_con0;
+	u32 dcc_cpu_con1;
+	u32 rsv_2588[6];
+	u32 dcc_bus_con0;
+	u32 rsv_25a4[7];
+	u32 mcusys_dcm_cfg0;
+	u32 rsv_25c4[79];
+	u32 fcm_spmc_sw_cfg1;
+	u32 fcm_spmc_sw_cfg2;
+	u32 fcm_spmc_wait_cfg;
+	u32 fcm_spmc_sw_pchannel;
+	u32 fcm_spmc_pwr_status;
+	u32 fcm_spmc_off_thres;
+	u32 fcm_spmc_wdt_latch_info;
+	u32 rsv_271c[9];
+	u32 mcusys_spmc_sw_cfg;
+	u32 mcusys_spmc_wait_cfg;
+	u32 mcusys_spmc_pwr_status;
+	u32 rsv_274c[45];
+	u32 cpc_pllbuck_req_ctrl;
+	u32 mcusys_pwr_ctrl;
+	u32 cpusys_pwr_ctrl;
+	u32 sw_gic_wakeup_req;
+	u32 cpc_pllbuck_arb_weight;
+	u32 cpc_flow_ctrl_cfg;
+	u32 cpc_last_core_req;
+	u32 cpc_cpusys_last_core_resp;
+	u32 rsv_2820;
+	u32 cpc_mcusys_last_core_resp;
+	u32 cpc_pwr_on_mask;
+	u32 rsv_282c[5];
+	u32 cpc_spmc_pwr_status;
+	u32 cpc_core_cur_fsm;
+	u32 cpc_cpusys_mcusys_cur_fsm;
+	u32 cpc_wakeup_req;
+	u32 rsv_2850;
+	u32 cpc_gp0_gp1_status;
+	u32 rsv_2858;
+	u32 cpc_turbo_ctrl;
+	u32 cpc_turbo_gp0_ctrl;
+	u32 cpc_turbo_gp1_ctrl;
+	u32 cpc_turbo_gp2_ctrl;
+	u32 cpc_turbo_pwr_on_mask;
+	u32 cpc_turbo_gp0_req;
+	u32 cpc_turbo_gp1_req;
+	u32 cpc_turbo_gp2_req;
+	u32 rsv_287c;
+	u32 cpc_turbo_gp0_resp;
+	u32 cpc_turbo_gp1_resp;
+	u32 cpc_turbo_gp2_resp;
+	u32 cpc_coh_block_thres;
+	u32 cpc_int_status;
+	u32 cpc_int_enable;
+	u32 pllbuck_group_func;
+	u32 cpc_dcm_enable;
+	u32 cpc_pllbuck_state;
+	u32 cpc_cpu_on_sw_hint;
+	u32 cpc_cpu_on_sw_hint_set;
+	u32 cpc_cpu_on_sw_hint_clear;
+	u32 rsv_28b0[20];
+	u32 emi_wfifo;
+	u32 axi1to4_cfg;
+	u32 apb_cfg;
+	u32 emi_adb_edge_sel;
+	u32 rsv_2910[4];
+	u32 sclk_cfg_slow_down_ck;
+	u32 rsv_2924[3];
+	u32 acpwakeup;
+	u32 rsv_2934;
+	u32 l3gic_idle_bypass;
+	u32 rsv_293c[21];
+	u32 mcusys_dbg_mon_sel;
+	u32 mcusys_dbg_mon;
+	u32 rsv_2998[27];
+	u32 lkg_mon_sw;
+	u32 lkg_mon_en;
+	u32 rsv_2a0c[29];
+	u32 gic_acao_ctl0;
+	u32 rsv_2a84;
+	u32 gic_acao_ctl2;
+	u32 rsv_2a8c[29];
+	u32 spmc_dbg_setting;
+	u32 kernel_base_l;
+	u32 kernel_base_h;
+	u32 systime_base_l;
+	u32 systime_base_h;
+	u32 trace_data_selection;
+	u32 rsv_2b18[2];
+	u32 trace_data_entry0_l;
+	u32 trace_data_entry0_h;
+	u32 trace_data_entry1_l;
+	u32 trace_data_entry1_h;
+	u32 trace_data_entry2_l;
+	u32 trace_data_entry2_h;
+	u32 trace_data_entry3_l;
+	u32 trace_data_entry3_h;
+	u32 cpu0_on_off_latency;
+	u32 cpu1_on_off_latency;
+	u32 cpu2_on_off_latency;
+	u32 cpu3_on_off_latency;
+	u32 cpu4_on_off_latency;
+	u32 cpu5_on_off_latency;
+	u32 cpu6_on_off_latency;
+	u32 cpu7_on_off_latency;
+	u32 cluster_off_latency;
+	u32 cluster_on_latency;
+	u32 mcusys_on_off_latency;
+	u32 rsv_2b6c;
+	u32 cluster_off_dormant_counter;
+	u32 cluster_off_dormant_counter_clear;
+	u32 turbo_gp0_gp1_latency;
+	u32 turbo_gp2_latency;
+	u32 cpc_wdt_latch_info1;
+	u32 cpc_wdt_latch_info2;
+	u32 cpc_wdt_latch_info3;
+	u32 cpc_wdt_latch_info4;
+	u32 cpc_wdt_latch_info5;
+	u32 cpc_pmu_ctrl;
+	u32 cpc_pmu_cnt_clr;
+	u32 cpc_pmu_cnt0;
+	u32 rsv_2ba0[4];
+	u32 cpc_wdt_latch_info6;
+	u32 cpc_wdt_latch_info7;
+	u32 cpc_ptm_event_en_ctrl;
+	u32 cpc_ptm_event_en_ctrl1;
+	u32 cpc_ptm_trace_sel;
+	u32 cpc_ptm_trace_status_l;
+	u32 cpc_ptm_trace_status_h;
+	u32 rsv_2bcc[29];
+	u32 sesv6_bg_ctrl;
+	u32 rsv_2c44[3];
+	u32 dsu_sesv6_ao_reg0;
+	u32 dsu_sesv6_ao_reg1;
+	u32 dsu_sesv6_ao_reg2;
+	u32 dsu_sesv6_ao_reg3;
+	u32 dsu_sesv6_ao_reg4;
+	u32 rsv_2c64[39];
+	u32 ildo_dout_sel;
+	u32 rsv_2d04[31];
+	u32 dreq20_little_en;
+	u32 rsv_2d84[2];
+	u32 dreq20_big_vproc_iso;
+	u32 rsv_2d90[28];
+	u32 pikachu_event;
+	u32 pikachu_status;
+	u32 rsv_2e08[126];
+	u32 cpu0_drcc_ao_config;
+	u32 rsv_3004[3];
+	u32 cpu0_sesv6_ao_reg0;
+	u32 cpu0_sesv6_ao_reg1;
+	u32 cpu0_sesv6_ao_reg2;
+	u32 cpu0_sesv6_ao_reg3;
+	u32 cpu0_sesv6_ao_reg4;
+	u32 rsv_3024[7];
+	u32 cpu0_dfs_cfg;
+	u32 rsv_3044[3];
+	u32 cpu0_turbo_cfg;
+	u32 rsv_3054[105];
+	u32 cpu0_resereved_reg;
+	u32 cpu0_resereved_reg_rd;
+	u32 cpu1_drcc_ao_config;
+	u32 rsv_3204[3];
+	u32 cpu1_sesv6_ao_reg0;
+	u32 cpu1_sesv6_ao_reg1;
+	u32 cpu1_sesv6_ao_reg2;
+	u32 cpu1_sesv6_ao_reg3;
+	u32 cpu1_sesv6_ao_reg4;
+	u32 rsv_3224[7];
+	u32 cpu1_dfs_cfg;
+	u32 rsv_3244[3];
+	u32 cpu1_turbo_cfg;
+	u32 rsv_3254[105];
+	u32 cpu1_resereved_reg;
+	u32 cpu1_resereved_reg_rd;
+	u32 cpu2_drcc_ao_config;
+	u32 rsv_3404[3];
+	u32 cpu2_sesv6_ao_reg0;
+	u32 cpu2_sesv6_ao_reg1;
+	u32 cpu2_sesv6_ao_reg2;
+	u32 cpu2_sesv6_ao_reg3;
+	u32 cpu2_sesv6_ao_reg4;
+	u32 rsv_3424[7];
+	u32 cpu2_dfs_cfg;
+	u32 rsv_3444[3];
+	u32 cpu2_turbo_cfg;
+	u32 rsv_3454[105];
+	u32 cpu2_resereved_reg;
+	u32 cpu2_resereved_reg_rd;
+	u32 cpu3_drcc_ao_config;
+	u32 rsv_3604[3];
+	u32 cpu3_sesv6_ao_reg0;
+	u32 cpu3_sesv6_ao_reg1;
+	u32 cpu3_sesv6_ao_reg2;
+	u32 cpu3_sesv6_ao_reg3;
+	u32 cpu3_sesv6_ao_reg4;
+	u32 rsv_3624[7];
+	u32 cpu3_dfs_cfg;
+	u32 rsv_3644[3];
+	u32 cpu3_turbo_cfg;
+	u32 rsv_3654[105];
+	u32 cpu3_resereved_reg;
+	u32 cpu3_resereved_reg_rd;
+	u32 cpu4_drcc_ao_config;
+	u32 rsv_3804[3];
+	u32 cpu4_sesv6_ao_reg0;
+	u32 cpu4_sesv6_ao_reg1;
+	u32 cpu4_sesv6_ao_reg2;
+	u32 cpu4_sesv6_ao_reg3;
+	u32 cpu4_sesv6_ao_reg4;
+	u32 rsv_3824[3];
+	u32 cpu4_didt_reg;
+	u32 rsv_3834[3];
+	u32 cpu4_dfs_cfg;
+	u32 rsv_3844[3];
+	u32 cpu4_turbo_cfg;
+	u32 rsv_3854[105];
+	u32 cpu4_resereved_reg;
+	u32 cpu4_resereved_reg_rd;
+	u32 cpu5_drcc_ao_config;
+	u32 rsv_3a04[3];
+	u32 cpu5_sesv6_ao_reg0;
+	u32 cpu5_sesv6_ao_reg1;
+	u32 cpu5_sesv6_ao_reg2;
+	u32 cpu5_sesv6_ao_reg3;
+	u32 cpu5_sesv6_ao_reg4;
+	u32 rsv_3a24[3];
+	u32 cpu5_didt_reg;
+	u32 rsv_3a34[3];
+	u32 cpu5_dfs_cfg;
+	u32 rsv_3a44[3];
+	u32 cpu5_turbo_cfg;
+	u32 rsv_3a54[105];
+	u32 cpu5_resereved_reg;
+	u32 cpu5_resereved_reg_rd;
+	u32 cpu6_drcc_ao_config;
+	u32 rsv_3c04[3];
+	u32 cpu6_sesv6_ao_reg0;
+	u32 cpu6_sesv6_ao_reg1;
+	u32 cpu6_sesv6_ao_reg2;
+	u32 cpu6_sesv6_ao_reg3;
+	u32 cpu6_sesv6_ao_reg4;
+	u32 rsv_3c24[3];
+	u32 cpu6_didt_reg;
+	u32 cpu6_mem_lre_reg;
+	u32 rsv_3c38[2];
+	u32 cpu6_dfs_cfg;
+	u32 rsv_3c44[3];
+	u32 cpu6_turbo_cfg;
+	u32 rsv_3c54[105];
+	u32 cpu6_resereved_reg;
+	u32 cpu6_resereved_reg_rd;
+	u32 cpu7_drcc_ao_config;
+	u32 rsv_3e04[3];
+	u32 cpu7_sesv6_ao_reg0;
+	u32 cpu7_sesv6_ao_reg1;
+	u32 cpu7_sesv6_ao_reg2;
+	u32 cpu7_sesv6_ao_reg3;
+	u32 cpu7_sesv6_ao_reg4;
+	u32 rsv_3e24[3];
+	u32 cpu7_didt_reg;
+	u32 cpu7_mem_lre_reg;
+	u32 rsv_3e38[2];
+	u32 cpu7_dfs_cfg;
+	u32 rsv_3e44[3];
+	u32 cpu7_turbo_cfg;
+	u32 rsv_3e54[105];
+	u32 cpu7_resereved_reg;
+	u32 cpu7_resereved_reg_rd;
+	u32 rsv_4000[512];
+	u32 mp0_mbist_cfg;
+	u32 rsv_4804[15];
+	u32 mp0_l3_data_ram_delsel;
+	u32 mp0_l3_tag_ram_delsel;
+	u32 mp0_l3_victim_ram_delsel;
+	u32 mp0_l3_scu_sf_ram_delsel;
+	u32 rsv_4850[12];
+	u32 mp0_dcm_cfg0;
+	u32 mp0_dcm_cfg1;
+	u32 mp0_dcm_cfg2;
+	u32 mp0_dcm_cfg3;
+	u32 mp0_dcm_cfg4;
+	u32 mp0_dcm_cfg5;
+	u32 mp0_dcm_cfg6;
+	u32 mp0_dcm_cfg7;
+	u32 mp0_dcm_cfg8;
+	u32 rsv_48a4[7];
+	u32 mp0_l3_cache_parity1;
+	u32 mp0_l3_cache_parity2;
+	u32 mp0_l3_cache_parity3;
+	u32 rsv_48cc;
+	u32 mp0_cluster_cfg0;
+	u32 rsv_48d4[3];
+	u32 mp0_cluster_cfg4;
+	u32 mp0_cluster_cfg5;
+	u32 mp0_cluster_cfg6;
+	u32 mp0_cluster_cfg7;
+	u32 rsv_48f0[4];
+	u32 mp0_cluster_cfg8;
+	u32 mp0_cluster_cfg9;
+	u32 mp0_cluster_cfg10;
+	u32 mp0_cluster_cfg11;
+	u32 mp0_cluster_cfg12;
+	u32 mp0_cluster_cfg13;
+	u32 mp0_cluster_cfg14;
+	u32 mp0_cluster_cfg15;
+	u32 mp0_cluster_cfg16;
+	u32 mp0_cluster_cfg17;
+	u32 mp0_cluster_cfg18;
+	u32 mp0_cluster_cfg19;
+	u32 mp0_cluster_cfg20;
+	u32 mp0_cluster_cfg21;
+	u32 mp0_cluster_cfg22;
+	u32 mp0_cluster_cfg23;
+	u32 mp0_mem_dreq_cfg;
+	u32 mp0_victim_rd_mask;
+	u32 mp0_minidcc_enable;
+	u32 mp0_mem_lv_mode;
+	u32 rsv_4950[172];
+	u32 cpu_type0_spmc0_cfg;
+	u32 rsv_4c04[7];
+	u32 cpu_type0_ram_delsel0_cfg;
+	u32 cpu_type0_ram_delsel1_cfg;
+	u32 cpu_type0_ram_delsel2_cfg;
+	u32 cpu_type0_ram_delsel3_cfg;
+	u32 rsv_4c30[52];
+	u32 cpu_type1_spmc0_cfg;
+	u32 rsv_4d04[3];
+	u32 cpu_type1_mpmmen;
+	u32 cpu_ppmctl;
+	u32 cpu_typex_most_on_mode;
+	u32 rsv_4d1c;
+	u32 cpu_type1_ram_delsel0_cfg;
+	u32 cpu_type1_ram_delsel1_cfg;
+	u32 cpu_type1_ram_delsel2_cfg;
+	u32 cpu_type1_ram_delsel3_cfg;
+	u32 rsv_4d30[4];
+	u32 cpu_type1_drss_cfg0;
+	u32 cpu_type1_drss_cfg1;
+	u32 rsv_4d48[54];
+	u32 cpu_type2_ram_delsel0_cfg;
+	u32 cpu_type2_ram_delsel1_cfg;
+	u32 cpu_type2_ram_delsel2_cfg;
+	u32 cpu_type2_ram_delsel3_cfg;
+	u32 rsv_4e30[244];
+	u32 mcusys_pwr_con;
+	u32 mp0_cputop_pwr_con;
+	u32 mp0_cpu0_pwr_con;
+	u32 mp0_cpu1_pwr_con;
+	u32 mp0_cpu2_pwr_con;
+	u32 mp0_cpu3_pwr_con;
+	u32 mp0_cpu4_pwr_con;
+	u32 mp0_cpu5_pwr_con;
+	u32 mp0_cpu6_pwr_con;
+	u32 mp0_cpu7_pwr_con;
+	u32 rsv_5228[246];
+	u32 sec_pol_ctl_en0;
+	u32 sec_pol_ctl_en1;
+	u32 sec_pol_ctl_en2;
+	u32 sec_pol_ctl_en3;
+	u32 sec_pol_ctl_en4;
+	u32 sec_pol_ctl_en5;
+	u32 sec_pol_ctl_en6;
+	u32 sec_pol_ctl_en7;
+	u32 sec_pol_ctl_en8;
+	u32 sec_pol_ctl_en9;
+	u32 sec_pol_ctl_en10;
+	u32 sec_pol_ctl_en11;
+	u32 sec_pol_ctl_en12;
+	u32 sec_pol_ctl_en13;
+	u32 sec_pol_ctl_en14;
+	u32 sec_pol_ctl_en15;
+	u32 sec_pol_ctl_en16;
+	u32 sec_pol_ctl_en17;
+	u32 sec_pol_ctl_en18;
+	u32 sec_pol_ctl_en19;
+	u32 sec_pol_ctl_en20;
+	u32 sec_pol_ctl_en21;
+	u32 sec_pol_ctl_en22;
+	u32 sec_pol_ctl_en23;
+	u32 sec_pol_ctl_en24;
+	u32 sec_pol_ctl_en25;
+	u32 sec_pol_ctl_en26;
+	u32 sec_pol_ctl_en27;
+	u32 sec_pol_ctl_en28;
+	u32 sec_pol_ctl_en29;
+	u32 sec_pol_ctl_en30;
+	u32 sec_pol_ctl_en31;
+	u32 int_pol_ctl0;
+	u32 int_pol_ctl1;
+	u32 int_pol_ctl2;
+	u32 int_pol_ctl3;
+	u32 int_pol_ctl4;
+	u32 int_pol_ctl5;
+	u32 int_pol_ctl6;
+	u32 int_pol_ctl7;
+	u32 int_pol_ctl8;
+	u32 int_pol_ctl9;
+	u32 int_pol_ctl10;
+	u32 int_pol_ctl11;
+	u32 int_pol_ctl12;
+	u32 int_pol_ctl13;
+	u32 int_pol_ctl14;
+	u32 int_pol_ctl15;
+	u32 int_pol_ctl16;
+	u32 int_pol_ctl17;
+	u32 int_pol_ctl18;
+	u32 int_pol_ctl19;
+	u32 int_pol_ctl20;
+	u32 int_pol_ctl21;
+	u32 int_pol_ctl22;
+	u32 int_pol_ctl23;
+	u32 int_pol_ctl24;
+	u32 int_pol_ctl25;
+	u32 int_pol_ctl26;
+	u32 int_pol_ctl27;
+	u32 int_pol_ctl28;
+	u32 int_pol_ctl29;
+	u32 int_pol_ctl30;
+	u32 int_pol_ctl31;
+	u32 int_msk_ctl0;
+	u32 int_msk_ctl1;
+	u32 int_msk_ctl2;
+	u32 int_msk_ctl3;
+	u32 int_msk_ctl4;
+	u32 int_msk_ctl5;
+	u32 int_msk_ctl6;
+	u32 int_msk_ctl7;
+	u32 int_msk_ctl8;
+	u32 int_msk_ctl9;
+	u32 int_msk_ctl10;
+	u32 int_msk_ctl11;
+	u32 int_msk_ctl12;
+	u32 int_msk_ctl13;
+	u32 int_msk_ctl14;
+	u32 int_msk_ctl15;
+	u32 int_msk_ctl16;
+	u32 int_msk_ctl17;
+	u32 int_msk_ctl18;
+	u32 int_msk_ctl19;
+	u32 int_msk_ctl20;
+	u32 int_msk_ctl21;
+	u32 int_msk_ctl22;
+	u32 int_msk_ctl23;
+	u32 int_msk_ctl24;
+	u32 int_msk_ctl25;
+	u32 int_msk_ctl26;
+	u32 int_msk_ctl27;
+	u32 int_msk_ctl28;
+	u32 int_msk_ctl29;
+	u32 int_msk_ctl30;
+	u32 int_msk_ctl31;
+	u32 int_msk_ctl_all;
+	u32 int_cfg_indirect_access;
+	u32 int_cfg_direct_access_en;
+	u32 rsv_578c[557];
+	u32 dfd_internal_ctl;
+	u32 dfd_internal_counter;
+	u32 dfd_internal_pwr_on;
+	u32 dfd_internal_chain_legth_0;
+	u32 dfd_internal_shift_clk_ratio;
+	u32 dfd_internal_counter_return;
+	u32 dfd_internal_sram_access;
+	u32 dfd_finish_wait_time;
+	u32 dfd_internal_chain_group;
+	u32 dfd_internal_chain_inv_info_ll;
+	u32 dfd_internal_chain_inv_info_lh;
+	u32 dfd_internal_chain_inv_info_hl;
+	u32 dfd_internal_chain_inv_info_hh;
+	u32 dfd_internal_test_so_over_64;
+	u32 dfd_internal_mask_out;
+	u32 dfd_internal_sw_ns_trigger;
+	u32 dfd_internal_mcsi;
+	u32 dfd_internal_mcsi_sel_status;
+	u32 dfd_v30_ctl;
+	u32 dfd_v30_base_addr;
+	u32 dfd_power_ctl;
+	u32 dfd_reset_on;
+	u32 dfd_test_si_0;
+	u32 dfd_test_si_1;
+	u32 dfd_status_clean;
+	u32 dfd_status_return;
+	u32 dfd_v35_enable;
+	u32 dfd_v35_tap_number;
+	u32 dfd_v35_tap_en;
+	u32 dfd_v35_ctl;
+	u32 dfd_v35_tap_seq0;
+	u32 dfd_v35_tap_seq1;
+	u32 dfd_v35_seq0_0;
+	u32 dfd_v35_seq0_1;
+	u32 dfd_v35_seq1_0;
+	u32 dfd_v35_seq1_1;
+	u32 dfd_v35_seq2_0;
+	u32 dfd_v35_seq2_1;
+	u32 rsv_60d8[6];
+	u32 dfd_soc_clock_stop_mask;
+	u32 rsv_60f4[2];
+	u32 dfd_hw_trigger_mask;
+	u32 dfd_v50_enable;
+	u32 dfd_v50_self_trigger_iteration;
+	u32 dfd_v50_start_trigger;
+	u32 dfd_v50_cpuck_halt;
+	u32 dfd_v50_26m_resume;
+	u32 dfd_v50_26m_halt_release;
+	u32 dfd_v50_system_halt_time;
+	u32 dfd_v50_group_0_1_diff;
+	u32 dfd_v50_group_0_2_diff;
+	u32 dfd_v50_group_0_3_diff;
+	u32 dfd_v50_group_0_4_diff;
+	u32 dfd_v50_group_0_5_diff;
+	u32 dfd_v50_group_0_6_diff;
+	u32 dfd_v50_group_0_7_diff;
+	u32 dfd_v50_group_0_8_diff;
+	u32 dfd_v50_group_0_9_diff;
+	u32 dfd_v50_group_0_10_diff;
+	u32 dfd_v50_group_0_11_diff;
+	u32 dfd_v50_group_0_12_diff;
+	u32 dfd_v50_group_0_13_diff;
+	u32 dfd_v50_group_0_14_diff;
+	u32 dfd_v50_group_0_15_diff;
+	u32 dfd_v50_group_0_16_diff;
+	u32 dfd_v50_group_0_17_diff;
+	u32 dfd_v50_group_0_18_diff;
+	u32 dfd_v50_group_0_19_diff;
+	u32 dfd_v50_group_0_20_diff;
+	u32 dfd_v50_group_0_21_diff;
+	u32 dfd_v50_group_0_22_diff;
+	u32 dfd_v50_group_0_23_diff;
+	u32 dfd_v50_group_0_24_diff;
+	u32 dfd_v50_group_0_25_diff;
+	u32 dfd_v50_group_0_26_diff;
+	u32 dfd_v50_group_0_27_diff;
+	u32 dfd_v50_group_0_28_diff;
+	u32 dfd_v50_group_0_29_diff;
+	u32 dfd_v50_group_0_30_diff;
+	u32 dfd_v50_group_0_31_diff;
+	u32 dfd_v50_chain_group_3_0_info;
+	u32 dfd_v50_chain_group_7_4_info;
+	u32 dfd_v50_chain_group_11_8_info;
+	u32 dfd_v50_chain_group_15_12_info;
+	u32 dfd_v50_chain_group_19_16_info;
+	u32 dfd_v50_chain_group_23_20_info;
+	u32 dfd_v50_chain_group_27_24_info;
+	u32 dfd_v50_chain_group_31_28_info;
+	u32 dfd_v50_chain_group_35_32_info;
+	u32 dfd_v50_chain_group_39_36_info;
+	u32 dfd_v50_chain_group_43_40_info;
+	u32 dfd_v50_chain_group_47_44_info;
+	u32 dfd_v50_chain_group_51_48_info;
+	u32 dfd_v50_chain_group_55_52_info;
+	u32 dfd_v50_chain_group_59_56_info;
+	u32 dfd_v50_chain_group_63_60_info;
+	u32 dfd_v50_chain_group_67_64_info;
+	u32 dfd_v50_chain_group_71_68_info;
+	u32 dfd_v50_chain_group_75_72_info;
+	u32 dfd_v50_chain_group_79_76_info;
+	u32 dfd_v50_chain_group_83_80_info;
+	u32 dfd_v50_chain_group_87_84_info;
+	u32 dfd_v50_chain_group_91_88_info;
+	u32 dfd_v50_chain_group_95_92_info;
+	u32 dfd_v50_chain_group_99_96_info;
+	u32 dfd_v50_chain_group_103_100_info;
+	u32 dfd_v50_chain_group_107_104_info;
+	u32 dfd_v50_chain_group_111_108_info;
+	u32 dfd_v50_chain_group_115_112_info;
+	u32 dfd_v50_chain_group_119_116_info;
+	u32 dfd_v50_chain_group_123_120_info;
+	u32 dfd_v50_chain_group_127_124_info;
+	u32 dfd_test_si_2;
+	u32 dfd_test_si_3;
+	u32 dfd_test_so;
+	u32 dfd_bus_halt_time;
+	u32 dfd_read_addr;
+	u32 dfd_v50_clk_stop_time;
+	u32 dfd_v50_group_0_32_diff;
+	u32 dfd_v50_group_0_33_diff;
+	u32 dfd_v50_group_0_34_diff;
+	u32 dfd_v50_group_0_35_diff;
+	u32 dfd_v50_group_0_36_diff;
+	u32 dfd_v50_group_0_37_diff;
+	u32 dfd_v50_group_0_38_diff;
+	u32 dfd_v50_group_0_39_diff;
+	u32 dfd_v50_group_0_40_diff;
+	u32 dfd_v50_group_0_41_diff;
+	u32 dfd_v50_group_0_42_diff;
+	u32 dfd_v50_group_0_43_diff;
+	u32 dfd_v50_group_0_44_diff;
+	u32 dfd_v50_group_0_45_diff;
+	u32 dfd_v50_group_0_46_diff;
+	u32 dfd_v50_group_0_47_diff;
+	u32 dfd_v50_group_0_48_diff;
+	u32 dfd_v50_group_0_49_diff;
+	u32 dfd_v50_group_0_50_diff;
+	u32 dfd_v50_group_0_51_diff;
+	u32 dfd_v50_group_0_52_diff;
+	u32 dfd_v50_group_0_53_diff;
+	u32 dfd_v50_group_0_54_diff;
+	u32 dfd_v50_group_0_55_diff;
+	u32 dfd_v50_group_0_56_diff;
+	u32 dfd_v50_group_0_57_diff;
+	u32 dfd_v50_group_0_58_diff;
+	u32 dfd_v50_group_0_59_diff;
+	u32 dfd_v50_group_0_60_diff;
+	u32 dfd_v50_group_0_61_diff;
+	u32 dfd_v50_group_0_62_diff;
+	u32 dfd_v50_group_0_63_diff;
+	u32 rsv_62b0[20];
+	u32 dfd_v50_spare;
+	u32 rsv_6304[1843];
+	u32 mcusys_reserved_reg4;
+	u32 mcusys_reserved_reg4_rd;
+	u32 rsv_7fd8[2];
+	u32 mcusys_reserved_reg0;
+	u32 mcusys_reserved_reg1;
+	u32 mcusys_reserved_reg2;
+	u32 mcusys_reserved_reg3;
+	u32 mcusys_reserved_reg0_rd;
+	u32 mcusys_reserved_reg1_rd;
+	u32 mcusys_reserved_reg2_rd;
+	u32 mcusys_reserved_reg3_rd;
+};
+
+check_member(mt8195_mcucfg_regs, cpu_plldiv_cfg0, 0x22a0);
+check_member(mt8195_mcucfg_regs, bus_plldiv_cfg, 0x22e0);
+
+static struct mt8195_mcucfg_regs *const mt8195_mcucfg = (void *)MCUCFG_BASE;
+
+#endif  /* SOC_MEDIATEK_MT8195_MCUCFG_H */
diff --git a/src/soc/mediatek/mt8195/include/soc/pll.h b/src/soc/mediatek/mt8195/include/soc/pll.h
index e2240ed195..6d836f7e8f 100644
--- a/src/soc/mediatek/mt8195/include/soc/pll.h
+++ b/src/soc/mediatek/mt8195/include/soc/pll.h
@@ -502,6 +502,63 @@ check_member(mtk_apmixed_regs, occscan_con4, 0x0d80);
 check_member(mtk_apmixed_regs, apll1_con5, 0x0dc0);
 check_member(mtk_apmixed_regs, hdmirx_apll_con5, 0x0dd4);
 
+enum {
+	PLL_CKSQ_ON_DELAY = 100,
+	PLL_PWR_ON_DELAY = 30,
+	PLL_ISO_DELAY = 1,
+	PLL_EN_DELAY = 20,
+};
+
+enum {
+	PCW_INTEGER_BITS = 8,
+};
+
+enum {
+	MT8195_PLL_EN = 0x1 << 9,
+	MT8195_APLL5_EN = (0x1 << 9) | (0x1 << 20),
+	GLITCH_FREE_EN = 0x1 << 12,
+	PLL_DIV_EN = 0xff << 24,
+};
+
+enum {
+	MCU_DIV_MASK = 0x1f << 17,
+	MCU_DIV_1 = 0x8 << 17,
+
+	MCU_MUX_MASK = 0x3 << 9,
+	MCU_MUX_SRC_PLL = 0x1 << 9,
+	MCU_MUX_SRC_26M = 0x0 << 9,
+};
+
+/* PLL rate */
+enum {
+	ARMPLL_LL_HZ	= 1036 * MHz,
+	ARMPLL_BL_HZ	= 1027 * MHz,
+	CCIPLL_HZ	= 835 * MHz,
+	NNAPLL_HZ	= 860 * MHz,
+	RESPLL_HZ	= 600 * MHz,
+	ETHPLL_HZ	= 500 * MHz,
+	MSDCPLL_HZ	= 384 * MHz,
+	TVDPLL1_HZ	= 594 * MHz,
+	TVDPLL2_HZ	= 594 * MHz,
+	MMPLL_HZ	= 2750UL * MHz,
+	MAINPLL_HZ	= 2184UL * MHz,
+	VDECPLL_HZ	= 220 * MHz,
+	IMGPLL_HZ	= 650 * MHz,
+	UNIVPLL_HZ	= 2496UL * MHz,
+	HDMIPLL1_HZ	= 884 * MHz,
+	HDMIPLL2_HZ	= 600 * MHz,
+	HDMIRX_APLL_HZ	= 294915 * KHz,
+	USB1PLL_HZ	= 192 * MHz,
+	ADSPPLL_HZ	= 720 * MHz,
+	APLL1_HZ	= 196608 * KHz,
+	APLL2_HZ	= 180633600,
+	APLL3_HZ	= 196608 * KHz,
+	APLL4_HZ	= 196608 * KHz,
+	APLL5_HZ	= 196608 * KHz,
+	MFGPLL_HZ	= 700 * MHz,
+	DGIPLL_HZ	= 165 * MHz,
+};
+
 /* top_div rate */
 enum {
 	CLK26M_HZ	= 26 * MHz,
@@ -512,4 +569,12 @@ enum {
 	UART_HZ		= CLK26M_HZ,
 };
 
+DEFINE_BITFIELD(CLK_DBG_CFG_ABIST_CK_SEL, 14, 8)
+DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_CK_SEL, 23, 16)
+DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0)
+DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_EN, 24, 24)
+DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24)
+DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4)
+DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16)
+
 #endif /* SOC_MEDIATEK_MT8195_PLL_H */
diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c
new file mode 100644
index 0000000000..6e85def9c2
--- /dev/null
+++ b/src/soc/mediatek/mt8195/pll.c
@@ -0,0 +1,836 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <delay.h>
+#include <stddef.h>
+#include <timer.h>
+
+#include <soc/addressmap.h>
+#include <soc/infracfg.h>
+#include <soc/mcucfg.h>
+#include <soc/pll.h>
+#include <soc/spm.h>
+#include <soc/wdt.h>
+
+struct mt8195_infracfg_ao_bcrm_regs {
+	u32 reserved1[13];
+	u32 vdnr_dcm_top_infra_ctrl0;	/* 0x0034 */
+};
+check_member(mt8195_infracfg_ao_bcrm_regs, vdnr_dcm_top_infra_ctrl0, 0x0034);
+static struct mt8195_infracfg_ao_bcrm_regs *const mt8195_infracfg_ao_bcrm =
+	(void *)INFRACFG_AO_BCRM_BASE;
+
+struct mt8195_pericfg_ao_regs {
+	u32 reserved1[4];
+	u32 peri_module_sw_cg_0_set;	/* 0x0010 */
+};
+check_member(mt8195_pericfg_ao_regs, peri_module_sw_cg_0_set, 0x0010);
+static struct mt8195_pericfg_ao_regs *const mt8195_pericfg_ao = (void *)PERICFG_AO_BASE;
+
+enum mux_id {
+	TOP_AXI_SEL,
+	TOP_SPM_SEL,
+	TOP_SCP_SEL,
+	TOP_BUS_AXIMEM_SEL,
+	TOP_VPP_SEL,
+	TOP_ETHDR_SEL,
+	TOP_IPE_SEL,
+	TOP_CAM_SEL,
+	TOP_CCU_SEL,
+	TOP_IMG_SEL,
+	TOP_CAMTM_SEL,
+	TOP_DSP_SEL,
+	TOP_DSP1_SEL,
+	TOP_DSP2_SEL,
+	TOP_DSP3_SEL,
+	TOP_DSP4_SEL,
+	TOP_DSP5_SEL,
+	TOP_DSP6_SEL,
+	TOP_DSP7_SEL,
+	TOP_IPU_IF_SEL,
+	TOP_MFG_SEL,
+	TOP_CAMTG_SEL,
+	TOP_CAMTG2_SEL,
+	TOP_CAMTG3_SEL,
+	TOP_CAMTG4_SEL,
+	TOP_CAMTG5_SEL,
+	TOP_UART_SEL,
+	TOP_SPI_SEL,
+	TOP_SPIS_SEL,
+	TOP_MSDC50_0_H_SEL,
+	TOP_MSDC50_0_SEL,
+	TOP_MSDC30_1_SEL,
+	TOP_MSDC30_2_SEL,
+	TOP_INTDIR_SEL,
+	TOP_AUD_INTBUS_SEL,
+	TOP_AUDIO_H_SEL,
+	TOP_PWRAP_ULPOSC_SEL,
+	TOP_ATB_SEL,
+	TOP_PWRMCU_SEL,
+	TOP_DP_SEL,
+	TOP_EDP_SEL,
+	TOP_DPI_SEL,
+	TOP_DISP_PWM0_SEL,
+	TOP_DISP_PWM1_SEL,
+	TOP_USB_SEL,
+	TOP_SSUSB_XHCI_SEL,
+	TOP_USB_1P_SEL,
+	TOP_SSUSB_XHCI_1P_SEL,
+	TOP_USB_2P_SEL,
+	TOP_SSUSB_XHCI_2P_SEL,
+	TOP_USB_3P_SEL,
+	TOP_SSUSB_XHCI_3P_SEL,
+	TOP_I2C_SEL,
+	TOP_SENINF_SEL,
+	TOP_SENINF1_SEL,
+	TOP_SENINF2_SEL,
+	TOP_SENINF3_SEL,
+	TOP_GCPU_SEL,
+	TOP_DXCC_SEL,
+	TOP_DPMAIF_SEL,
+	TOP_AES_UFSFDE_SEL,
+	TOP_UFS_SEL,
+	TOP_UFS_TICK1US_SEL,
+	TOP_UFS_MP_SAP_SEL,
+	TOP_VENC_SEL,
+	TOP_VDEC_SEL,
+	TOP_PWM_SEL,
+	TOP_MCUPM_SEL,
+	TOP_SPMI_P_MST_SEL,
+	TOP_SPMI_M_MST_SEL,
+	TOP_DVFSRC_SEL,
+	TOP_TL_SEL,
+	TOP_TL_P1_SEL,
+	TOP_AES_MSDCFDE_SEL,
+	TOP_DSI_OCC_SEL,
+	TOP_WPE_VPP_SEL,
+	TOP_HDCP_SEL,
+	TOP_HDCP_24M_SEL,
+	TOP_HD20_DACR_REF_SEL,
+	TOP_HD20_HDCP_C_SEL,
+	TOP_HDMI_XTAL_SEL,
+	TOP_HDMI_APB_SEL,
+	TOP_SNPS_ETH_250M_SEL,
+	TOP_SNPS_ETH_62P4M_PTP_SEL,
+	TOP_SNPS_ETH_50M_RMII_SEL,
+	TOP_DGI_OUT_SEL,
+	TOP_NNA0_SEL,
+	TOP_NNA1_SEL,
+	TOP_ADSP_SEL,
+	TOP_ASM_H_SEL,
+	TOP_ASM_M_SEL,
+	TOP_ASM_L_SEL,
+	TOP_APLL1_SEL,
+	TOP_APLL2_SEL,
+	TOP_APLL3_SEL,
+	TOP_APLL4_SEL,
+	TOP_APLL5_SEL,
+	TOP_I2SO1_M_SEL,
+	TOP_I2SO2_M_SEL,
+	TOP_I2SI1_M_SEL,
+	TOP_I2SI2_M_SEL,
+	TOP_DPTX_M_SEL,
+	TOP_AUD_IEC_SEL,
+	TOP_A1SYS_HP_SEL,
+	TOP_A2SYS_SEL,
+	TOP_A3SYS_SEL,
+	TOP_A4SYS_SEL,
+	TOP_SPINFI_B_SEL,
+	TOP_NFI1X_SEL,
+	TOP_ECC_SEL,
+	TOP_AUDIO_LOCAL_BUS_SEL,
+	TOP_SPINOR_SEL,
+	TOP_DVIO_DGI_REF_SEL,
+	TOP_SRCK_SEL,
+	TOP_RSVD1_SEL,
+	TOP_MFG_FAST_SEL,
+	TOP_NR_MUX
+};
+
+#define MUX(_id, _reg, _mux_shift, _mux_width)		\
+	[_id] = {					\
+		.reg = &mtk_topckgen->_reg,		\
+		.mux_shift = _mux_shift,		\
+		.mux_width = _mux_width,		\
+	}
+
+#define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\
+	[_id] = {							\
+		.reg = &mtk_topckgen->_reg,				\
+		.set_reg = &mtk_topckgen->_reg##_set,			\
+		.clr_reg = &mtk_topckgen->_reg##_clr,			\
+		.mux_shift = _mux_shift,				\
+		.mux_width = _mux_width,				\
+		.upd_reg = &mtk_topckgen->_upd_reg,			\
+		.upd_shift = _upd_shift,				\
+	}
+
+static const struct mux muxes[] = {
+	/* CLK_CFG_0 */
+	MUX_UPD(TOP_AXI_SEL, clk_cfg_0, 0, 3, clk_cfg_update, 0),
+	MUX_UPD(TOP_SPM_SEL, clk_cfg_0, 8, 2, clk_cfg_update, 1),
+	MUX_UPD(TOP_SCP_SEL, clk_cfg_0, 16, 3, clk_cfg_update, 2),
+	MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, 24, 3, clk_cfg_update, 3),
+	/* CLK_CFG_1 */
+	MUX_UPD(TOP_VPP_SEL, clk_cfg_1, 0, 4, clk_cfg_update, 4),
+	MUX_UPD(TOP_ETHDR_SEL, clk_cfg_1, 8, 4, clk_cfg_update, 5),
+	MUX_UPD(TOP_IPE_SEL, clk_cfg_1, 16, 4, clk_cfg_update, 6),
+	MUX_UPD(TOP_CAM_SEL, clk_cfg_1, 24, 4, clk_cfg_update, 7),
+	/* CLK_CFG_2 */
+	MUX_UPD(TOP_CCU_SEL, clk_cfg_2, 0, 4, clk_cfg_update, 8),
+	MUX_UPD(TOP_IMG_SEL, clk_cfg_2, 8, 4, clk_cfg_update, 9),
+	MUX_UPD(TOP_CAMTM_SEL, clk_cfg_2, 16, 2, clk_cfg_update, 10),
+	MUX_UPD(TOP_DSP_SEL, clk_cfg_2, 24, 3, clk_cfg_update, 11),
+	/* CLK_CFG_3 */
+	MUX_UPD(TOP_DSP1_SEL, clk_cfg_3, 0, 3, clk_cfg_update, 12),
+	MUX_UPD(TOP_DSP2_SEL, clk_cfg_3, 8, 3, clk_cfg_update, 13),
+	MUX_UPD(TOP_DSP3_SEL, clk_cfg_3, 16, 3, clk_cfg_update, 14),
+	MUX_UPD(TOP_DSP4_SEL, clk_cfg_3, 24, 3, clk_cfg_update, 15),
+	/* CLK_CFG_4 */
+	MUX_UPD(TOP_DSP5_SEL, clk_cfg_4, 0, 3, clk_cfg_update, 16),
+	MUX_UPD(TOP_DSP6_SEL, clk_cfg_4, 8, 3, clk_cfg_update, 17),
+	MUX_UPD(TOP_DSP7_SEL, clk_cfg_4, 16, 3, clk_cfg_update, 18),
+	MUX_UPD(TOP_IPU_IF_SEL, clk_cfg_4, 24, 3, clk_cfg_update, 19),
+	/* CLK_CFG_5 */
+	MUX_UPD(TOP_MFG_SEL, clk_cfg_5, 0, 2, clk_cfg_update, 20),
+	MUX_UPD(TOP_CAMTG_SEL, clk_cfg_5, 8, 3, clk_cfg_update, 21),
+	MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_5, 16, 3, clk_cfg_update, 22),
+	MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_5, 24, 3, clk_cfg_update, 23),
+	/* CLK_CFG_6 */
+	MUX_UPD(TOP_CAMTG4_SEL, clk_cfg_6, 0, 3, clk_cfg_update, 24),
+	MUX_UPD(TOP_CAMTG5_SEL, clk_cfg_6, 8, 3, clk_cfg_update, 25),
+	MUX_UPD(TOP_UART_SEL, clk_cfg_6, 16, 1, clk_cfg_update, 26),
+	MUX_UPD(TOP_SPI_SEL, clk_cfg_6, 24, 3, clk_cfg_update, 27),
+	/* CLK_CFG_7 */
+	MUX_UPD(TOP_SPIS_SEL, clk_cfg_7, 0, 3, clk_cfg_update, 28),
+	MUX_UPD(TOP_MSDC50_0_H_SEL, clk_cfg_7, 8, 2, clk_cfg_update, 29),
+	MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_7, 16, 3, clk_cfg_update, 30),
+	MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_7, 24, 3, clk_cfg_update, 31),
+	/* CLK_CFG_8 */
+	MUX_UPD(TOP_MSDC30_2_SEL, clk_cfg_8, 0, 3, clk_cfg_update1, 0),
+	MUX_UPD(TOP_INTDIR_SEL, clk_cfg_8, 8, 2, clk_cfg_update1, 1),
+	MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_8, 16, 2, clk_cfg_update1, 2),
+	MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_8, 24, 2, clk_cfg_update1, 3),
+	/* CLK_CFG_9 */
+	MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_9, 0, 3, clk_cfg_update1, 4),
+	MUX_UPD(TOP_ATB_SEL, clk_cfg_9, 8, 2, clk_cfg_update1, 5),
+	MUX_UPD(TOP_PWRMCU_SEL, clk_cfg_9, 16, 3, clk_cfg_update1, 6),
+	MUX_UPD(TOP_DP_SEL, clk_cfg_9, 24, 4, clk_cfg_update1, 7),
+	/* CLK_CFG_10 */
+	MUX_UPD(TOP_EDP_SEL, clk_cfg_10, 0, 4, clk_cfg_update1, 8),
+	MUX_UPD(TOP_DPI_SEL, clk_cfg_10, 8, 4, clk_cfg_update1, 9),
+	MUX_UPD(TOP_DISP_PWM0_SEL, clk_cfg_10, 16, 3, clk_cfg_update1, 10),
+	MUX_UPD(TOP_DISP_PWM1_SEL, clk_cfg_10, 24, 3, clk_cfg_update1, 11),
+	/* CLK_CFG_11 */
+	MUX_UPD(TOP_USB_SEL, clk_cfg_11, 0, 2, clk_cfg_update1, 12),
+	MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_11, 8, 2, clk_cfg_update1, 13),
+	MUX_UPD(TOP_USB_1P_SEL, clk_cfg_11, 16, 2, clk_cfg_update1, 14),
+	MUX_UPD(TOP_SSUSB_XHCI_1P_SEL, clk_cfg_11, 24, 2, clk_cfg_update1, 15),
+	/* CLK_CFG_12 */
+	MUX_UPD(TOP_USB_2P_SEL, clk_cfg_12, 0, 2, clk_cfg_update1, 16),
+	MUX_UPD(TOP_SSUSB_XHCI_2P_SEL, clk_cfg_12, 8, 2, clk_cfg_update1, 17),
+	MUX_UPD(TOP_USB_3P_SEL, clk_cfg_12, 16, 2, clk_cfg_update1, 18),
+	MUX_UPD(TOP_SSUSB_XHCI_3P_SEL, clk_cfg_12, 24, 2, clk_cfg_update1, 19),
+	/* CLK_CFG_13 */
+	MUX_UPD(TOP_I2C_SEL, clk_cfg_13, 0, 2, clk_cfg_update1, 20),
+	MUX_UPD(TOP_SENINF_SEL, clk_cfg_13, 8, 3, clk_cfg_update1, 21),
+	MUX_UPD(TOP_SENINF1_SEL, clk_cfg_13, 16, 3, clk_cfg_update1, 22),
+	MUX_UPD(TOP_SENINF2_SEL, clk_cfg_13, 24, 3, clk_cfg_update1, 23),
+	/* CLK_CFG_14 */
+	MUX_UPD(TOP_SENINF3_SEL, clk_cfg_14, 0, 3, clk_cfg_update1, 24),
+	MUX_UPD(TOP_GCPU_SEL, clk_cfg_14, 8, 3, clk_cfg_update1, 25),
+	MUX_UPD(TOP_DXCC_SEL, clk_cfg_14, 16, 2, clk_cfg_update1, 26),
+	MUX_UPD(TOP_DPMAIF_SEL, clk_cfg_14, 24, 3, clk_cfg_update1, 27),
+	/* CLK_CFG_15 */
+	MUX_UPD(TOP_AES_UFSFDE_SEL, clk_cfg_15, 0, 3, clk_cfg_update1, 28),
+	MUX_UPD(TOP_UFS_SEL, clk_cfg_15, 8, 3, clk_cfg_update1, 29),
+	MUX_UPD(TOP_UFS_TICK1US_SEL, clk_cfg_15, 16, 1, clk_cfg_update1, 30),
+	MUX_UPD(TOP_UFS_MP_SAP_SEL, clk_cfg_15, 24, 1, clk_cfg_update1, 31),
+	/* CLK_CFG_16 */
+	MUX_UPD(TOP_VENC_SEL, clk_cfg_16, 0, 4, clk_cfg_update2, 0),
+	MUX_UPD(TOP_VDEC_SEL, clk_cfg_16, 8, 4, clk_cfg_update2, 1),
+	MUX_UPD(TOP_PWM_SEL, clk_cfg_16, 16, 1, clk_cfg_update2, 2),
+	MUX_UPD(TOP_MCUPM_SEL, clk_cfg_16, 24, 2, clk_cfg_update2, 3),
+	/* CLK_CFG_17 */
+	MUX_UPD(TOP_SPMI_P_MST_SEL, clk_cfg_17, 0, 4, clk_cfg_update2, 4),
+	MUX_UPD(TOP_SPMI_M_MST_SEL, clk_cfg_17, 8, 4, clk_cfg_update2, 5),
+	MUX_UPD(TOP_DVFSRC_SEL, clk_cfg_17, 16, 2, clk_cfg_update2, 6),
+	MUX_UPD(TOP_TL_SEL, clk_cfg_17, 24, 2, clk_cfg_update2, 7),
+	/* CLK_CFG_18 */
+	MUX_UPD(TOP_TL_P1_SEL, clk_cfg_18, 0, 2, clk_cfg_update2, 8),
+	MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_18, 8, 3, clk_cfg_update2, 9),
+	MUX_UPD(TOP_DSI_OCC_SEL, clk_cfg_18, 16, 2, clk_cfg_update2, 10),
+	MUX_UPD(TOP_WPE_VPP_SEL, clk_cfg_18, 24, 4, clk_cfg_update2, 11),
+	/* CLK_CFG_19 */
+	MUX_UPD(TOP_HDCP_SEL, clk_cfg_19, 0, 2, clk_cfg_update2, 12),
+	MUX_UPD(TOP_HDCP_24M_SEL, clk_cfg_19, 8, 2, clk_cfg_update2, 13),
+	MUX_UPD(TOP_HD20_DACR_REF_SEL, clk_cfg_19, 16, 2, clk_cfg_update2, 14),
+	MUX_UPD(TOP_HD20_HDCP_C_SEL, clk_cfg_19, 24, 2, clk_cfg_update2, 15),
+	/* CLK_CFG_20 */
+	MUX_UPD(TOP_HDMI_XTAL_SEL, clk_cfg_20, 0, 1, clk_cfg_update2, 16),
+	MUX_UPD(TOP_HDMI_APB_SEL, clk_cfg_20, 8, 2, clk_cfg_update2, 17),
+	MUX_UPD(TOP_SNPS_ETH_250M_SEL, clk_cfg_20, 16, 1, clk_cfg_update2, 18),
+	MUX_UPD(TOP_SNPS_ETH_62P4M_PTP_SEL, clk_cfg_20, 24, 2, clk_cfg_update2, 19),
+	/* CLK_CFG_21 */
+	MUX_UPD(TOP_SNPS_ETH_50M_RMII_SEL, clk_cfg_21, 0, 1, clk_cfg_update2, 20),
+	MUX_UPD(TOP_DGI_OUT_SEL, clk_cfg_21, 8, 3, clk_cfg_update2, 21),
+	MUX_UPD(TOP_NNA0_SEL, clk_cfg_21, 16, 4, clk_cfg_update2, 22),
+	MUX_UPD(TOP_NNA1_SEL, clk_cfg_21, 24, 4, clk_cfg_update2, 23),
+	/* CLK_CFG_22 */
+	MUX_UPD(TOP_ADSP_SEL, clk_cfg_22, 0, 4, clk_cfg_update2, 24),
+	MUX_UPD(TOP_ASM_H_SEL, clk_cfg_22, 8, 2, clk_cfg_update2, 25),
+	MUX_UPD(TOP_ASM_M_SEL, clk_cfg_22, 16, 2, clk_cfg_update2, 26),
+	MUX_UPD(TOP_ASM_L_SEL, clk_cfg_22, 24, 2, clk_cfg_update2, 27),
+	/* CLK_CFG_23 */
+	MUX_UPD(TOP_APLL1_SEL, clk_cfg_23, 0, 1, clk_cfg_update2, 28),
+	MUX_UPD(TOP_APLL2_SEL, clk_cfg_23, 8, 1, clk_cfg_update2, 29),
+	MUX_UPD(TOP_APLL3_SEL, clk_cfg_23, 16, 1, clk_cfg_update2, 30),
+	MUX_UPD(TOP_APLL4_SEL, clk_cfg_23, 24, 1, clk_cfg_update2, 31),
+	/* CLK_CFG_24 */
+	MUX_UPD(TOP_APLL5_SEL, clk_cfg_24, 0, 1, clk_cfg_update3, 0),
+	MUX_UPD(TOP_I2SO1_M_SEL, clk_cfg_24, 8, 3, clk_cfg_update3, 1),
+	MUX_UPD(TOP_I2SO2_M_SEL, clk_cfg_24, 16, 3, clk_cfg_update3, 2),
+	/* CLK_CFG_25 */
+	MUX_UPD(TOP_I2SI1_M_SEL, clk_cfg_25, 8, 3, clk_cfg_update3, 5),
+	MUX_UPD(TOP_I2SI2_M_SEL, clk_cfg_25, 16, 3, clk_cfg_update3, 6),
+	/* CLK_CFG_26 */
+	MUX_UPD(TOP_DPTX_M_SEL, clk_cfg_26, 8, 3, clk_cfg_update3, 9),
+	MUX_UPD(TOP_AUD_IEC_SEL, clk_cfg_26, 16, 3, clk_cfg_update3, 10),
+	MUX_UPD(TOP_A1SYS_HP_SEL, clk_cfg_26, 24, 1, clk_cfg_update3, 11),
+	/* CLK_CFG_27 */
+	MUX_UPD(TOP_A2SYS_SEL, clk_cfg_27, 0, 1, clk_cfg_update3, 12),
+	MUX_UPD(TOP_A3SYS_SEL, clk_cfg_27, 8, 3, clk_cfg_update3, 13),
+	MUX_UPD(TOP_A4SYS_SEL, clk_cfg_27, 16, 3, clk_cfg_update3, 14),
+	MUX_UPD(TOP_SPINFI_B_SEL, clk_cfg_27, 24, 3, clk_cfg_update3, 15),
+	/* CLK_CFG_28 */
+	MUX_UPD(TOP_NFI1X_SEL, clk_cfg_28, 0, 3, clk_cfg_update3, 16),
+	MUX_UPD(TOP_ECC_SEL, clk_cfg_28, 8, 3, clk_cfg_update3, 17),
+	MUX_UPD(TOP_AUDIO_LOCAL_BUS_SEL, clk_cfg_28, 16, 4, clk_cfg_update3, 18),
+	MUX_UPD(TOP_SPINOR_SEL, clk_cfg_28, 24, 2, clk_cfg_update3, 19),
+	/* CLK_CFG_29 */
+	MUX_UPD(TOP_DVIO_DGI_REF_SEL, clk_cfg_29, 0, 3, clk_cfg_update3, 20),
+	MUX_UPD(TOP_SRCK_SEL, clk_cfg_29, 24, 1, clk_cfg_update3, 23),
+	/* CLK_CFG_37 */
+	MUX_UPD(TOP_RSVD1_SEL, clk_cfg_37, 0, 3, clk_cfg_update4, 20),
+	/* CLK_MISC_CFG_3 */
+	MUX(TOP_MFG_FAST_SEL, clk_misc_cfg_3, 8, 1),
+};
+
+struct mux_sel {
+	enum mux_id id;
+	u32 sel;
+};
+
+static const struct mux_sel mux_sels[] = {
+	/* CLK_CFG_0 */
+	{ .id = TOP_AXI_SEL, .sel = 2 },			/* 2: mainpll_d7_d2 */
+	/* CLK_CFG_37 */
+	{ .id = TOP_RSVD1_SEL, .sel = 2 },			/* 2: mainpll_d5_d4 */
+	/* CLK_CFG_0 */
+	{ .id = TOP_SPM_SEL, .sel = 2 },			/* 2: mainpll_d7_d4 */
+	{ .id = TOP_SCP_SEL, .sel = 7 },			/* 7: mainpll_d6_d2 */
+	{ .id = TOP_BUS_AXIMEM_SEL, .sel = 3 },			/* 3: mainpll_d5_d2 */
+	/* CLK_CFG_1 */
+	{ .id = TOP_VPP_SEL, .sel = 2 },			/* 2: mainpll_d5_d2 */
+	{ .id = TOP_ETHDR_SEL, .sel = 10 },			/* 10: mmpll_d5_d4 */
+	{ .id = TOP_IPE_SEL, .sel = 8 },			/* 8: mainpll_d4_d2 */
+	{ .id = TOP_CAM_SEL, .sel = 8 },			/* 8: mainpll_d4_d2 */
+	/* CLK_CFG_2 */
+	{ .id = TOP_CCU_SEL, .sel = 2 },			/* 2: mainpll_d4_d2 */
+	{ .id = TOP_IMG_SEL, .sel = 11 },			/* 11: univpll_d5_d2 */
+	{ .id = TOP_CAMTM_SEL, .sel = 2 },			/* 2: univpll_d6_d2 */
+	{ .id = TOP_DSP_SEL, .sel = 7 },			/* 7: univpll_d3 */
+	/* CLK_CFG_3 */
+	{ .id = TOP_DSP1_SEL, .sel = 7 },			/* 7: univpll_d3 */
+	{ .id = TOP_DSP2_SEL, .sel = 7 },			/* 7: univpll_d3 */
+	{ .id = TOP_DSP3_SEL, .sel = 7 },			/* 7: univpll_d3 */
+	{ .id = TOP_DSP4_SEL, .sel = 7 },			/* 7: univpll_d3 */
+	/* CLK_CFG_4 */
+	{ .id = TOP_DSP5_SEL, .sel = 7 },			/* 7: univpll_d3 */
+	{ .id = TOP_DSP6_SEL, .sel = 7 },			/* 7: univpll_d3 */
+	{ .id = TOP_DSP7_SEL, .sel = 7 },			/* 7: univpll_d3 */
+	{ .id = TOP_IPU_IF_SEL, .sel = 7 },			/* 7: mmpll_d4 */
+	/* CLK_CFG_5 */
+	{ .id = TOP_MFG_SEL, .sel = 3 },			/* 3: univpll_d7 */
+	{ .id = TOP_CAMTG_SEL, .sel = 2 },			/* 2: univpll_d6_d8 */
+	{ .id = TOP_CAMTG2_SEL, .sel = 2 },			/* 2: univpll_d6_d8 */
+	{ .id = TOP_CAMTG3_SEL, .sel = 2 },			/* 2: univpll_d6_d8 */
+	/* CLK_CFG_6 */
+	{ .id = TOP_CAMTG4_SEL, .sel = 2 },			/* 2: univpll_d6_d8 */
+	{ .id = TOP_CAMTG5_SEL, .sel = 2 },			/* 2: univpll_d6_d8 */
+	{ .id = TOP_UART_SEL, .sel = 0 },			/* 0: xtal_26m_ck */
+	{ .id = TOP_SPI_SEL, .sel = 4 },			/* 4: univpll_d6_d2 */
+	/* CLK_CFG_7 */
+	{ .id = TOP_SPIS_SEL, .sel = 1 },			/* 1: univpll_d6 */
+	{ .id = TOP_MSDC50_0_H_SEL, .sel = 1 },			/* 1: mainpll_d4_d2 */
+	{ .id = TOP_MSDC50_0_SEL, .sel = 1 },			/* 1: msdcpll_ck */
+	{ .id = TOP_MSDC30_1_SEL, .sel = 1 },			/* 1: univpll_d6_d2 */
+	/* CLK_CFG_8 */
+	{ .id = TOP_MSDC30_2_SEL, .sel = 1 },			/* 1: univpll_d6_d2 */
+	{ .id = TOP_INTDIR_SEL, .sel = 3 },			/* 3: univpll_d4 */
+	{ .id = TOP_AUD_INTBUS_SEL, .sel = 1 },			/* 1: mainpll_d4_d4 */
+	{ .id = TOP_AUDIO_H_SEL, .sel = 2 },			/* 2: apll1_ck */
+	/* CLK_CFG_9 */
+	{ .id = TOP_PWRAP_ULPOSC_SEL, .sel = 1 },		/* 1: clk26m  */
+	{ .id = TOP_ATB_SEL, .sel = 1 },			/* 1: mainpll_d4_d2 */
+	{ .id = TOP_PWRMCU_SEL, .sel = 3 },			/* 3: mainpll_d5_d2 */
+	{ .id = TOP_DP_SEL, .sel = 3 },				/* 3: tvdpll1_d4 */
+	/* CLK_CFG_10 */
+	{ .id = TOP_EDP_SEL, .sel = 3 },			/* 3: tvdpll1_d4 */
+	{ .id = TOP_DPI_SEL, .sel = 1 },			/* 1: tvdpll1_d2 */
+	{ .id = TOP_DISP_PWM0_SEL, .sel = 1 },			/* 1: univpll_d6_d4 */
+	{ .id = TOP_DISP_PWM1_SEL, .sel = 1 },			/* 1: univpll_d6_d4 */
+	/* CLK_CFG_11 */
+	{ .id = TOP_USB_SEL, .sel = 1 },			/* 1: univpll_d5_d4 */
+	{ .id = TOP_SSUSB_XHCI_SEL, .sel = 1 },			/* 1: univpll_d5_d4 */
+	{ .id = TOP_USB_1P_SEL, .sel = 1 },			/* 1: univpll_d5_d4 */
+	{ .id = TOP_SSUSB_XHCI_1P_SEL, .sel = 1 },		/* 1: univpll_d5_d4 */
+	/* CLK_CFG_12 */
+	{ .id = TOP_USB_2P_SEL, .sel = 1 },			/* 1: univpll_d5_d4 */
+	{ .id = TOP_SSUSB_XHCI_2P_SEL, .sel = 1 },		/* 1: univpll_d5_d4 */
+	{ .id = TOP_USB_3P_SEL, .sel = 1 },			/* 1: univpll_d5_d4 */
+	{ .id = TOP_SSUSB_XHCI_3P_SEL, .sel = 1 },		/* 1: univpll_d5_d4 */
+	/* CLK_CFG_13 */
+	{ .id = TOP_I2C_SEL, .sel = 2 },			/* 2: univpll_d5_d4 */
+	{ .id = TOP_SENINF_SEL, .sel = 4 },			/* 4: univpll_d7 */
+	{ .id = TOP_SENINF1_SEL, .sel = 4 },			/* 4: univpll_d7 */
+	{ .id = TOP_SENINF2_SEL, .sel = 4 },			/* 4: univpll_d7 */
+	/* CLK_CFG_14 */
+	{ .id = TOP_SENINF3_SEL, .sel = 4 },			/* 4: univpll_d7 */
+	{ .id = TOP_GCPU_SEL, .sel = 3 },			/* 3: mmpll_d5_d2 */
+	{ .id = TOP_DXCC_SEL, .sel = 1 },			/* 1: mainpll_d4_d2 */
+	{ .id = TOP_DPMAIF_SEL, .sel = 3 },			/* 3: mainpll_d4_d2 */
+	/* CLK_CFG_15 */
+	{ .id = TOP_AES_UFSFDE_SEL, .sel = 5 },			/* 5: univpll_d6 */
+	{ .id = TOP_UFS_SEL, .sel = 6 },			/* 6: msdcpll_d2 */
+	{ .id = TOP_UFS_TICK1US_SEL, .sel = 0 },		/* 0: xtal_26m_d52 */
+	{ .id = TOP_UFS_MP_SAP_SEL, .sel = 0 },			/* 0: xtal_26m_ck */
+	/* CLK_CFG_16 */
+	{ .id = TOP_VENC_SEL, .sel = 14 },			/* 14: univpll_d5_d2 */
+	{ .id = TOP_VDEC_SEL, .sel = 1 },			/* 1: mainpll_d5_d2 */
+	{ .id = TOP_PWM_SEL, .sel = 1 },			/* 1: univpll_d4_d8 */
+	{ .id = TOP_MCUPM_SEL, .sel = 1 },			/* 1: mainpll_d6_d2 */
+	/* CLK_CFG_17 */
+	{ .id = TOP_SPMI_P_MST_SEL, .sel = 7 },			/* 7: mainpll_d7_d8 */
+	{ .id = TOP_SPMI_M_MST_SEL, .sel = 7 },			/* 7: mainpll_d7_d8 */
+	{ .id = TOP_DVFSRC_SEL, .sel = 0 },			/* 0: xtal_26m_ck */
+	{ .id = TOP_TL_SEL, .sel = 2 },				/* 2: mainpll_d4_d4 */
+	/* CLK_CFG_18 */
+	{ .id = TOP_TL_P1_SEL, .sel = 2 },			/* 2: mainpll_d4_d4 */
+	{ .id = TOP_AES_MSDCFDE_SEL, .sel = 5 },		/* 5: univpll_d6 */
+	{ .id = TOP_DSI_OCC_SEL, .sel = 1 },			/* 1: mainpll_d6_d2 */
+	{ .id = TOP_WPE_VPP_SEL, .sel = 4 },			/* 4: mainpll_d4_d2 */
+	/* CLK_CFG_19 */
+	{ .id = TOP_HDCP_SEL, .sel = 3 },			/* 3: univpll_d6_d4 */
+	{ .id = TOP_HDCP_24M_SEL, .sel = 2 },			/* 2: univpll_192m_d8 */
+	{ .id = TOP_HD20_DACR_REF_SEL, .sel = 1 },		/* 1: univpll_d4_d2 */
+	{ .id = TOP_HD20_HDCP_C_SEL, .sel = 1 },		/* 1: msdcpll_d4 */
+	/* CLK_CFG_20 */
+	{ .id = TOP_HDMI_XTAL_SEL, .sel = 0 },			/* 0: xtal_26m_ck */
+	{ .id = TOP_HDMI_APB_SEL, .sel = 2 },			/* 2: msdcpll_d2 */
+	{ .id = TOP_SNPS_ETH_250M_SEL, .sel = 1 },		/* 1: ethpll_d2 */
+	{ .id = TOP_SNPS_ETH_62P4M_PTP_SEL, .sel = 3 },		/* 3: ethpll_d8 */
+	/* CLK_CFG_21 */
+	{ .id = TOP_SNPS_ETH_50M_RMII_SEL, .sel = 1 },		/* 1: ethpll_d10 */
+	{ .id = TOP_DGI_OUT_SEL, .sel = 5 },			/* 5: mmpll_d4_d4 */
+	{ .id = TOP_NNA0_SEL, .sel = 1 },			/* 1: nnapll_ck */
+	{ .id = TOP_NNA1_SEL, .sel = 1 },			/* 1: nnapll_ck */
+	/* CLK_CFG_22 */
+	{ .id = TOP_ADSP_SEL, .sel = 8 },			/* 8: adsppll_ck */
+	{ .id = TOP_ASM_H_SEL, .sel = 3 },			/* 3: mainpll_d5_d2 */
+	{ .id = TOP_ASM_M_SEL, .sel = 3 },			/* 3: mainpll_d5_d2 */
+	{ .id = TOP_ASM_L_SEL, .sel = 3 },			/* 3: mainpll_d5_d2 */
+	/* CLK_CFG_23 */
+	{ .id = TOP_APLL1_SEL, .sel = 1 },			/* 1: apll1_d4 */
+	{ .id = TOP_APLL2_SEL, .sel = 1 },			/* 1: apll2_d4 */
+	{ .id = TOP_APLL3_SEL, .sel = 1 },			/* 1: apll3_d4 */
+	{ .id = TOP_APLL4_SEL, .sel = 1 },			/* 1: apll4_d4 */
+	/* CLK_CFG_24 */
+	{ .id = TOP_APLL5_SEL, .sel = 1 },			/* 1: apll5_d4 */
+	{ .id = TOP_I2SO1_M_SEL, .sel = 6 },			/* 6: hdmirx_apll_ck */
+	{ .id = TOP_I2SO2_M_SEL, .sel = 6 },			/* 6: hdmirx_apll_ck */
+	/* CLK_CFG_25 */
+	{ .id = TOP_I2SI1_M_SEL, .sel = 6 },			/* 6: hdmirx_apll_ck */
+	{ .id = TOP_I2SI2_M_SEL, .sel = 6 },			/* 6: hdmirx_apll_ck */
+	/* CLK_CFG_26 */
+	{ .id = TOP_DPTX_M_SEL, .sel = 6 },			/* 6: hdmirx_apll_ck */
+	{ .id = TOP_AUD_IEC_SEL, .sel = 6 },			/* 6: hdmirx_apll_ck */
+	{ .id = TOP_A1SYS_HP_SEL, .sel = 1 },			/* 1: apll1_d4 */
+	/* CLK_CFG_27 */
+	{ .id = TOP_A2SYS_SEL, .sel = 1 },			/* 1: apll2_d4 */
+	{ .id = TOP_A3SYS_SEL, .sel = 1 },			/* 1: apll3_d4 */
+	{ .id = TOP_A4SYS_SEL, .sel = 2 },			/* 2: apll4_d4 */
+	{ .id = TOP_SPINFI_B_SEL, .sel = 7 },			/* 7: univpll_d5_d4 */
+	/* CLK_CFG_28 */
+	{ .id = TOP_NFI1X_SEL, .sel = 7 },			/* 7: mainpll_d6_d2 */
+	{ .id = TOP_ECC_SEL, .sel = 1 },			/* 1: mainpll_d4_d4 */
+	{ .id = TOP_AUDIO_LOCAL_BUS_SEL, .sel = 3 },		/* 3: mainpll_d7_d2 */
+	{ .id = TOP_SPINOR_SEL, .sel = 3 },			/* 3: univpll_d6_d8 */
+	/* CLK_CFG_29 */
+	{ .id = TOP_DVIO_DGI_REF_SEL, .sel = 1 },		/* 1: in_dgi_ck */
+	{ .id = TOP_SRCK_SEL, .sel = 1 },			/* 1: xtal_26m_ck */
+	/* CLK_MISC_CFG_3 */
+	{ .id = TOP_MFG_FAST_SEL, .sel = 1 },			/* 1: AD_MFGPLL_OPP_CK */
+};
+
+enum pll_id {
+	APMIXED_ARMPLL_LL,
+	APMIXED_ARMPLL_BL,
+	APMIXED_CCIPLL,
+	APMIXED_NNAPLL,
+	APMIXED_RESPLL,
+	APMIXED_ETHPLL,
+	APMIXED_MSDCPLL,
+	APMIXED_TVDPLL1,
+	APMIXED_TVDPLL2,
+	APMIXED_MMPLL,
+	APMIXED_MAINPLL,
+	APMIXED_VDECPLL,
+	APMIXED_IMGPLL,
+	APMIXED_UNIVPLL,
+	APMIXED_HDMIPLL1,
+	APMIXED_HDMIPLL2,
+	APMIXED_HDMIRX_APLL,
+	APMIXED_USB1PLL,
+	APMIXED_ADSPPLL,
+	APMIXED_APLL1,
+	APMIXED_APLL2,
+	APMIXED_APLL3,
+	APMIXED_APLL4,
+	APMIXED_APLL5,
+	APMIXED_MFGPLL,
+	APMIXED_DGIPLL,
+	APMIXED_PLL_MAX
+};
+
+static const u32 pll_div_rate[] = {
+	3800UL * MHz,
+	1900 * MHz,
+	950 * MHz,
+	475 * MHz,
+	237500 * KHz,
+	0,
+};
+
+static const struct pll plls[] = {
+	PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con4,
+	    NO_RSTB_SHIFT, 22, armpll_ll_con2, 24, armpll_ll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_ARMPLL_BL, armpll_bl_con0, armpll_bl_con4,
+	    NO_RSTB_SHIFT, 22, armpll_bl_con2, 24, armpll_bl_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con4,
+	    NO_RSTB_SHIFT, 22, ccipll_con2, 24, ccipll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_NNAPLL, nnapll_con0, nnapll_con4,
+	    NO_RSTB_SHIFT, 22, nnapll_con2, 24, nnapll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_RESPLL, respll_con0, respll_con4,
+	    NO_RSTB_SHIFT, 22, respll_con2, 24, respll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_ETHPLL, ethpll_con0, ethpll_con4,
+	    NO_RSTB_SHIFT, 22, ethpll_con2, 24, ethpll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con4,
+	    NO_RSTB_SHIFT, 22, msdcpll_con2, 24, msdcpll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_TVDPLL1, tvdpll1_con0, tvdpll1_con4,
+	    NO_RSTB_SHIFT, 22, tvdpll1_con2, 24, tvdpll1_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_TVDPLL2, tvdpll2_con0, tvdpll2_con4,
+	    NO_RSTB_SHIFT, 22, tvdpll2_con2, 24, tvdpll2_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con4,
+	    23, 22, mmpll_con2, 24, mmpll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con4,
+	    23, 22, mainpll_con2, 24, mainpll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_VDECPLL, vdecpll_con0, vdecpll_con4,
+	    NO_RSTB_SHIFT, 22, vdecpll_con2, 24, vdecpll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_IMGPLL, imgpll_con0, imgpll_con4,
+	    NO_RSTB_SHIFT, 22, imgpll_con2, 24, imgpll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_UNIVPLL, univpll_con0, univpll_con4,
+	    23, 22, univpll_con2, 24, univpll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_HDMIPLL1, hdmipll1_con0, hdmipll1_con4,
+	    NO_RSTB_SHIFT, 22, hdmipll1_con2, 24, hdmipll1_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_HDMIPLL2, hdmipll2_con0, hdmipll2_con4,
+	    NO_RSTB_SHIFT, 22, hdmipll2_con2, 24, hdmipll2_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_HDMIRX_APLL, hdmirx_apll_con0, hdmirx_apll_con5,
+	    NO_RSTB_SHIFT, 32, hdmirx_apll_con2, 24, hdmirx_apll_con3, 0,
+	    pll_div_rate),
+	PLL(APMIXED_USB1PLL, usb1pll_con0, usb1pll_con4,
+	    NO_RSTB_SHIFT, 22, usb1pll_con2, 24, usb1pll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con4,
+	    NO_RSTB_SHIFT, 22, adsppll_con2, 24, adsppll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_APLL1, apll1_con0, apll1_con5,
+	    NO_RSTB_SHIFT, 32, apll1_con2, 24, apll1_con3, 0,
+	    pll_div_rate),
+	PLL(APMIXED_APLL2, apll2_con0, apll2_con5,
+	    NO_RSTB_SHIFT, 32, apll2_con2, 24, apll2_con3, 0,
+	    pll_div_rate),
+	PLL(APMIXED_APLL3, apll3_con0, apll3_con5,
+	    NO_RSTB_SHIFT, 32, apll3_con2, 24, apll3_con3, 0,
+	    pll_div_rate),
+	PLL(APMIXED_APLL4, apll4_con0, apll4_con5,
+	    NO_RSTB_SHIFT, 32, apll4_con2, 24, apll4_con3, 0,
+	    pll_div_rate),
+	PLL(APMIXED_APLL5, apll5_con0, apll5_con5,
+	    NO_RSTB_SHIFT, 32, apll5_con2, 24, apll5_con3, 0,
+	    pll_div_rate),
+	PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con4,
+	    NO_RSTB_SHIFT, 22, mfgpll_con2, 24, mfgpll_con2, 0,
+	    pll_div_rate),
+	PLL(APMIXED_DGIPLL, dgipll_con0, dgipll_con4,
+	    NO_RSTB_SHIFT, 22, dgipll_con2, 24, dgipll_con2, 0,
+	    pll_div_rate),
+};
+
+struct rate {
+	enum pll_id id;
+	u32 rate;
+};
+
+static const struct rate rates[] = {
+	{ .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ },
+	{ .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ },
+	{ .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ },
+	{ .id = APMIXED_NNAPLL, .rate = NNAPLL_HZ },
+	{ .id = APMIXED_RESPLL, .rate = RESPLL_HZ },
+	{ .id = APMIXED_ETHPLL, .rate = ETHPLL_HZ },
+	{ .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ },
+	{ .id = APMIXED_TVDPLL1, .rate = TVDPLL1_HZ },
+	{ .id = APMIXED_TVDPLL2, .rate = TVDPLL2_HZ },
+	{ .id = APMIXED_MMPLL, .rate = MMPLL_HZ },
+	{ .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ },
+	{ .id = APMIXED_VDECPLL, .rate = VDECPLL_HZ },
+	{ .id = APMIXED_IMGPLL, .rate = IMGPLL_HZ },
+	{ .id = APMIXED_UNIVPLL, .rate = UNIVPLL_HZ },
+	{ .id = APMIXED_HDMIPLL1, .rate = HDMIPLL1_HZ },
+	{ .id = APMIXED_HDMIPLL2, .rate = HDMIPLL2_HZ },
+	{ .id = APMIXED_HDMIRX_APLL, .rate = HDMIRX_APLL_HZ },
+	{ .id = APMIXED_USB1PLL, .rate = USB1PLL_HZ },
+	{ .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ },
+	{ .id = APMIXED_APLL1, .rate = APLL1_HZ },
+	{ .id = APMIXED_APLL2, .rate = APLL2_HZ },
+	{ .id = APMIXED_APLL3, .rate = APLL3_HZ },
+	{ .id = APMIXED_APLL4, .rate = APLL4_HZ },
+	{ .id = APMIXED_APLL5, .rate = APLL5_HZ },
+	{ .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ },
+	{ .id = APMIXED_DGIPLL, .rate = DGIPLL_HZ },
+};
+
+void pll_set_pcw_change(const struct pll *pll)
+{
+	setbits32(pll->div_reg, PLL_PCW_CHG);
+}
+
+void mt_pll_init(void)
+{
+	int i;
+
+	/* enable clock square */
+	setbits32(&mtk_apmixed->ap_pll_con0, 0x4);
+
+	udelay(PLL_CKSQ_ON_DELAY);
+
+	/* enable clock square1 low-pass filter */
+	setbits32(&mtk_apmixed->ap_pll_con0, 0x2);
+
+	/* xPLL PWR ON */
+	for (i = 0; i < APMIXED_PLL_MAX; i++)
+		setbits32(plls[i].pwr_reg, PLL_PWR_ON);
+
+	udelay(PLL_PWR_ON_DELAY);
+
+	/* xPLL ISO Disable */
+	for (i = 0; i < APMIXED_PLL_MAX; i++)
+		clrbits32(plls[i].pwr_reg, PLL_ISO);
+
+	udelay(PLL_ISO_DELAY);
+
+	/* disable glitch free if rate < 374MHz */
+	for (i = 0; i < ARRAY_SIZE(rates); i++) {
+		if (rates[i].rate < 374 * MHz)
+			clrbits32(plls[rates[i].id].reg, GLITCH_FREE_EN);
+	}
+
+	/* disable mfg_ck_en[20], enable mfg_opp_ck_en[2]  */
+	clrbits32(&mtk_apmixed->mfgpll_con0, 0x1 << 20);
+	setbits32(&mtk_apmixed->mfgpll_con1, 0x1 << 2);
+
+	/* xPLL Frequency Set */
+	for (i = 0; i < ARRAY_SIZE(rates); i++)
+		pll_set_rate(&plls[rates[i].id], rates[i].rate);
+
+	/* AUDPLL Tuner Frequency Set */
+	write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con3) + 1);
+	write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con3) + 1);
+	write32(&mtk_apmixed->apll3_tuner_con0, read32(&mtk_apmixed->apll3_con3) + 1);
+	write32(&mtk_apmixed->apll4_tuner_con0, read32(&mtk_apmixed->apll4_con3) + 1);
+	write32(&mtk_apmixed->apll5_tuner_con0, read32(&mtk_apmixed->apll5_con3) + 1);
+
+	/* xPLL Frequency Enable */
+	for (i = 0; i < APMIXED_PLL_MAX; i++) {
+		if (i == APMIXED_APLL5)
+			setbits32(plls[i].pwr_reg, MT8195_APLL5_EN);
+		else
+			setbits32(plls[i].reg, MT8195_PLL_EN);
+	}
+
+	/* enable univpll analog divider=13 */
+	setbits32(&mtk_apmixed->univpll_con0, 0x8d);
+
+	/* wait for PLL stable */
+	udelay(PLL_EN_DELAY);
+
+	/* xPLL DIV Enable & RSTB */
+	for (i = 0; i < APMIXED_PLL_MAX; i++) {
+		if (plls[i].rstb_shift != NO_RSTB_SHIFT) {
+			setbits32(plls[i].reg, PLL_DIV_EN);
+			setbits32(plls[i].reg, 1 << plls[i].rstb_shift);
+		}
+	}
+
+	/* MCUCFG CLKMUX */
+	clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1);
+	clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1);
+	clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1);
+
+	clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+	clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+	clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+
+	/* enable infrasys DCM */
+	setbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl, 0x3 << 21);
+	setbits32(&mt8195_infracfg_ao_bcrm->vdnr_dcm_top_infra_ctrl0, 0x2);
+
+	/* initialize SPM request */
+	setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff);
+
+	/*
+	 * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
+	 */
+	for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
+		mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
+
+	/* switch sram control to bypass mode for PCIE_MAC_P0 */
+	setbits32(&mtk_spm->ap_mdsrc_req, 0x1);
+
+	/* ctitical clock */
+	write32(&mt8195_infracfg_ao->module_sw_cg_0_clr, 0x00000020);
+	write32(&mt8195_infracfg_ao->module_sw_cg_1_clr, 0x00100000);
+	write32(&mt8195_infracfg_ao->module_sw_cg_2_clr, 0x02000000);
+	write32(&mt8195_infracfg_ao->module_sw_cg_3_clr, 0x00000003);
+
+	/* turn off unused clock */
+	write32(&mt8195_pericfg_ao->peri_module_sw_cg_0_set, 0x10);
+}
+
+void mt_pll_raise_little_cpu_freq(u32 freq)
+{
+	/* switch clock source to intermediate clock */
+	clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M);
+
+	/* disable armpll_ll frequency output */
+	clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8195_PLL_EN);
+
+	/* raise armpll_ll frequency */
+	pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq);
+
+	/* enable armpll_ll frequency output */
+	setbits32(plls[APMIXED_ARMPLL_LL].reg, MT8195_PLL_EN);
+	udelay(PLL_EN_DELAY);
+
+	/* switch clock source back to armpll_ll */
+	clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+}
+
+void mt_pll_raise_cci_freq(u32 freq)
+{
+	/* switch clock source to intermediate clock */
+	clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M);
+
+	/* disable ccipll frequency output */
+	clrbits32(plls[APMIXED_CCIPLL].reg, MT8195_PLL_EN);
+
+	/* raise ccipll frequency */
+	pll_set_rate(&plls[APMIXED_CCIPLL], freq);
+
+	/* enable ccipll frequency output */
+	setbits32(plls[APMIXED_CCIPLL].reg, MT8195_PLL_EN);
+	udelay(PLL_EN_DELAY);
+
+	/* switch clock source back to ccipll */
+	clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+}
+
+u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
+{
+	u32 output, count, clk_dbg_cfg, clk_misc_cfg_0;
+
+	/* backup */
+	clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg);
+	clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0);
+
+	/* set up frequency meter */
+	if (type == FMETER_ABIST) {
+		SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg,
+				CLK_DBG_CFG_ABIST_CK_SEL, id,
+				CLK_DBG_CFG_CKGEN_CK_SEL, 0,
+				CLK_DBG_CFG_METER_CK_SEL, 0,
+				CLK_DBG_CFG_CKGEN_EN, 0);
+		SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
+				CLK_MISC_CFG_0_METER_DIV, 3);
+	} else if (type == FMETER_CKGEN) {
+		SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg,
+				CLK_DBG_CFG_ABIST_CK_SEL, 0,
+				CLK_DBG_CFG_CKGEN_CK_SEL, id,
+				CLK_DBG_CFG_METER_CK_SEL, 1,
+				CLK_DBG_CFG_CKGEN_EN, 1);
+		SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
+				CLK_MISC_CFG_0_METER_DIV, 0);
+	} else {
+		die("unsupport fmeter type\n");
+	}
+
+	/* enable frequency meter */
+	write32(&mtk_topckgen->clk26cali_0, 0x80);
+
+	/* set load count = 1024-1 */
+	SET32_BITFIELDS(&mtk_topckgen->clk26cali_1, CLK26CALI_1_LOAD_CNT, 0x3ff);
+
+	/* trigger frequency meter */
+	SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER, 1);
+
+	/* wait frequency meter until finished */
+	if (wait_us(200, !READ32_BITFIELD(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER))) {
+		count = read32(&mtk_topckgen->clk26cali_1) & 0xffff;
+		output = (count * 26000) / 1024; /* KHz */
+	} else {
+		printk(BIOS_WARNING, "fmeter timeout\n");
+		output = 0;
+	}
+
+	/* disable frequency meter */
+	write32(&mtk_topckgen->clk26cali_0, 0x0000);
+
+	/* restore */
+	write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg);
+	write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0);
+
+	if (type == FMETER_ABIST)
+		return output * 4;
+	else if (type == FMETER_CKGEN)
+		return output;
+
+	return 0;
+}