diff options
| author | Patrick Georgi <patrick@coreboot.org> | 2023-10-07 11:16:43 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@coreboot.org> | 2023-10-11 12:08:22 +0000 |
| commit | 42f15054b178efe9a4d1c8a4e0c203d1aa4aad01 (patch) | |
| tree | e1702953813d9c5c0930be4aca3d95b2aeecde00 /src/soc/mediatek | |
| parent | c666a916112aece345da57a0b4f3bafc43234ee7 (diff) | |
memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere
This is in preparation of a larger heap. I went for 2MB because why not?
Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/mt8173/memlayout.ld | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/memlayout.ld | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/memlayout.ld | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/memlayout.ld | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/memlayout.ld | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8195/include/soc/memlayout.ld | 2 |
6 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld index 8dce4284de..224dbdabaa 100644 --- a/src/soc/mediatek/mt8173/memlayout.ld +++ b/src/soc/mediatek/mt8173/memlayout.ld @@ -42,5 +42,5 @@ SECTIONS DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 1M) - RAMSTAGE(0x40200000, 256K) + RAMSTAGE(0x40200000, 2M) } diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld index 390842693f..c5d9d08324 100644 --- a/src/soc/mediatek/mt8183/memlayout.ld +++ b/src/soc/mediatek/mt8183/memlayout.ld @@ -44,7 +44,7 @@ SECTIONS DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 1M) - RAMSTAGE(0x40200000, 256K) + RAMSTAGE(0x40200000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld index f8bb0fa898..f927b608a8 100644 --- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld @@ -62,7 +62,7 @@ SECTIONS DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8188/include/soc/memlayout.ld b/src/soc/mediatek/mt8188/include/soc/memlayout.ld index 8d1f2bde65..ed3b71be07 100644 --- a/src/soc/mediatek/mt8188/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8188/include/soc/memlayout.ld @@ -66,7 +66,7 @@ SECTIONS DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 6c238c7d8f..b1beef0970 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -54,7 +54,7 @@ SECTIONS DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8195/include/soc/memlayout.ld b/src/soc/mediatek/mt8195/include/soc/memlayout.ld index 322844ded5..06806c508b 100644 --- a/src/soc/mediatek/mt8195/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8195/include/soc/memlayout.ld @@ -65,7 +65,7 @@ SECTIONS DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } |