diff options
author | Yidi Lin <yidi.lin@mediatek.com> | 2020-07-29 19:18:38 +0800 |
---|---|---|
committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-10 03:22:54 +0000 |
commit | f4bf8f5fab33e18eccde7c7db8eb9388cc286297 (patch) | |
tree | 591420f208b9c6e616abd4f017b9d63792512050 /src/soc/mediatek | |
parent | a5f472bf57e8897c4c47dce6050f0dfacfca5f13 (diff) |
soc/mediatek/mt8192: Load MCUPM firmware and boot up MCUPM
MCUPM is the MediaTek proprietary firmware for MCU power management.
TEST=1. emerge-asurada coreboot chromeos-bootimage;
2. See following log during booting.
load_blob_file: Load mcupm.bin in 35 msecs, size 115668 bytes
3. Test suspend/resume by:
a. suspend (on DUT): powerd_dbus_suspend
b. resume (on host): dut-control power_state:on
Change-Id: I50bea1942507b4a40df9730b4e1bf98980d74277
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46392
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek')
-rw-r--r-- | src/soc/mediatek/mt8192/Kconfig | 6 | ||||
-rw-r--r-- | src/soc/mediatek/mt8192/Makefile.inc | 2 | ||||
-rw-r--r-- | src/soc/mediatek/mt8192/include/soc/addressmap.h | 2 | ||||
-rw-r--r-- | src/soc/mediatek/mt8192/include/soc/mcupm.h | 14 | ||||
-rw-r--r-- | src/soc/mediatek/mt8192/mcupm.c | 33 | ||||
-rw-r--r-- | src/soc/mediatek/mt8192/soc.c | 2 |
6 files changed, 59 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index dbb35f6a98..36ad2e3e01 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -45,6 +45,12 @@ config MEMORY_TEST This option enables memory basic compare test to verify the DRAM read or write is as expected. +config MCUPM_FIRMWARE + string + default "mcupm.bin" + help + The file name of the MediaTek MCUPM firmware. + config SPM_FIRMWARE string default "spm_firmware.bin" diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 3caa1efe17..2fc8f39ee0 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -40,6 +40,7 @@ ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += ../common/mcu.c +ramstage-y += mcupm.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c @@ -51,6 +52,7 @@ ramstage-y += ../common/usb.c usb.c MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 mcu-firmware-files := \ + $(CONFIG_MCUPM_FIRMWARE) \ $(CONFIG_SPM_FIRMWARE) $(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 12094ffe5d..c68403b2b5 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -5,6 +5,8 @@ enum { MCUSYS_BASE = 0x0C530000, + MCUPM_SRAM_BASE = 0x0C540000, + MCUPM_CFG_BASE = 0x0C560000, IO_PHYS = 0x10000000, }; diff --git a/src/soc/mediatek/mt8192/include/soc/mcupm.h b/src/soc/mediatek/mt8192/include/soc/mcupm.h new file mode 100644 index 0000000000..dcb8c4a3e0 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mcupm.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_MCUPM_H +#define SOC_MEDIATEK_MT8192_MCUPM_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8192_mcupm_regs { + u32 sw_rstn; +}; +static struct mt8192_mcupm_regs *const mt8192_mcupm = (void *)MCUPM_CFG_BASE; +void mcupm_init(void); +#endif /* SOC_MEDIATEK_MT8192_MCUPM_H */ diff --git a/src/soc/mediatek/mt8192/mcupm.c b/src/soc/mediatek/mt8192/mcupm.c new file mode 100644 index 0000000000..70981a05ec --- /dev/null +++ b/src/soc/mediatek/mt8192/mcupm.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/mcu_common.h> +#include <soc/mcupm.h> +#include <soc/symbols.h> + +#define ABNORMALBOOT_REG 0x0C55FAA0 + +static void reset_mcupm(struct mtk_mcu *mcu) +{ + /* Clear abnormal boot register */ + write32((void *)ABNORMALBOOT_REG, 0x0); + write32(&mt8192_mcupm->sw_rstn, 0x1); +} + +static struct mtk_mcu mcupm = { + .firmware_name = CONFIG_MCUPM_FIRMWARE, + .run_address = (void *)MCUPM_SRAM_BASE, + .reset = reset_mcupm, +}; + +void mcupm_init(void) +{ + mcupm.load_buffer = _dram_dma; + mcupm.buffer_size = REGION_SIZE(dram_dma); + + write32(&mt8192_mcupm->sw_rstn, 0x0); + + if (mtk_init_mcu(&mcupm)) + die("%s() failed\n", __func__); +} diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 6978406cac..00a57d2f37 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <soc/emi.h> +#include <soc/mcupm.h> #include <soc/mmu_operations.h> #include <symbols.h> @@ -13,6 +14,7 @@ static void soc_read_resources(struct device *dev) static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + mcupm_init(); } static struct device_operations soc_ops = { |