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author | V Sowmya <v.sowmya@intel.com> | 2020-11-11 08:15:09 +0530 |
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committer | Furquan Shaikh <furquan@google.com> | 2020-11-18 01:26:30 +0000 |
commit | f2e8a7ae6bb228d43d88b4cd75ee33e0b72d36ab (patch) | |
tree | 1b49e0d559b6841a128f5ad34688ab3fb4dba9d9 /src/soc/mediatek | |
parent | 338b83c7b840198b537427ade46c54d7ddb217b1 (diff) |
mb/google/dedede: Modify flash layout to add ME_RW_A/B regions
Existing implementation adds the CSE RW update binary to FW_MAIN_A/B
regions and this has significant impact on boot time due to the
increase in the size of these regions leading to higher loading
and hashing time.
This patch modifies flash layout to add new ME_RW_A/B fmap regions
in the RW_SECTION_A/B.
BUG=b:169077783
TEST= Built for dedede. Verified that CSE RW binary is added to the
CSE_RW_A/B fmap region.
Change-Id: I23a3e22a569488b39beb4d12f5b6309c7c742992
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/mediatek')
0 files changed, 0 insertions, 0 deletions