diff options
| author | Yidi Lin <yidi.lin@mediatek.com> | 2020-09-22 19:56:20 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-11-18 06:13:03 +0000 |
| commit | 9ee02095fa1b5c532f758e287401423138687b56 (patch) | |
| tree | 04ebf5e626718032b75203c35219d84066dda28b /src/soc/mediatek | |
| parent | 9247d128390a70ab8ad5a2eba4ea73dc56a51375 (diff) | |
mb/google/asurada: Implement board-specific regulator controls
Currently, five regulator controls are implemented for DRAM
calibration and DVFS feature.
The regulators for VCORE and VM18 are controlled by MT6359.
The reguatlors for VDD1, VDD2 and VMDDR are controlled by MT6360
via EC.
BUG=b:147789962
BRANCH=none
TEST=verified with DRAM driver
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Id06a8196ca4badc51b06759afb07b5664278d13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/common/include/soc/regulator.h | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/mt6360.h | 16 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/mediatek/common/include/soc/regulator.h b/src/soc/mediatek/common/include/soc/regulator.h index 258d5503f1..6d9ff4e301 100644 --- a/src/soc/mediatek/common/include/soc/regulator.h +++ b/src/soc/mediatek/common/include/soc/regulator.h @@ -10,6 +10,7 @@ enum mtk_regulator { MTK_REGULATOR_VDD2, MTK_REGULATOR_VDDQ, MTK_REGULATOR_VMDDR, + MTK_REGULATOR_VCORE, }; void mainboard_set_regulator_vol(enum mtk_regulator regulator, diff --git a/src/soc/mediatek/mt8192/include/soc/mt6360.h b/src/soc/mediatek/mt8192/include/soc/mt6360.h new file mode 100644 index 0000000000..a6ee76c08b --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mt6360.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT6360_H__ +#define __SOC_MEDIATEK_MT6360_H__ + +enum mt6360_regulator_id { + MT6360_LDO3 = 0, + MT6360_LDO5, + MT6360_LDO6, + MT6360_LDO7, + MT6360_BUCK1, + MT6360_BUCK2, + MT6360_REGULATOR_COUNT, +}; + +#endif /* __SOC_MEDIATEK_MT6360_H__ */ |