soc/mediatek/mt8192: Add dramc ac timing setting

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I10e704868e4cd36a938a669879bb1a8632e73e1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

3 files changed, 1358 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
index 7f8d83a4d3..173edf44df 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
@@ -1,8 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <soc/dramc_ac_timing.h>
 #include <soc/dramc_pi_api.h>
 #include <soc/dramc_register.h>
 #include <soc/gpio.h>
+#include <string.h>
 #include <timer.h>
 
 static const u8 mrr_o1_pinmux_mapping[PINMUX_MAX][CHANNEL_MAX][DQ_DATA_WIDTH] = {
@@ -4033,6 +4035,206 @@ static void dramc_mode_reg_init(const struct ddr_cali *cali)
 	dramc_set_broadcast(bc_bak);
 }
 
+static void ddr_update_ac_timing(const struct ddr_cali *cali)
+{
+	u8 table_idx;
+	const struct ac_timing *ac_tim;
+	const dram_freq_grp freq_group = cali->freq_group;
+
+	u8 rank_inctl, tx_dly, datlat_dsel;
+	const u8 root = 0;
+	u8 tx_rank_inctl;
+	const u8 tref_bw = 0;
+	u8 tfaw_05t, trrd_05t;
+	u16 xrtwtw, xtrtrt, xrtw2r, xrtr2w, tfaw;
+	u16 trtw, trtw_05t, tmrr2w, trrd;
+	u16 phs_inctl;
+	u32 rank_inctl_root;
+
+	for (table_idx = 0; table_idx < AC_TIMING_NUMBER; table_idx++)
+		if (ac_timing_tbl[table_idx].freq_group == freq_group &&
+		     ac_timing_tbl[table_idx].div_mode == get_div_mode(cali) &&
+		     ac_timing_tbl[table_idx].cbt_mode == get_cbt_mode(cali)) {
+			dramc_dbg("Found matched AC timing table %u\n", table_idx);
+			break;
+		}
+
+	if (table_idx == AC_TIMING_NUMBER) {
+		dramc_err("Error: no matched AC timing table found\n");
+		return;
+	}
+
+	ac_tim = &ac_timing_tbl[table_idx];
+
+	trtw = ac_tim->trtw_odt_on;
+	trtw_05t = ac_tim->trtw_odt_on_05T;
+	xrtw2r = ac_tim->xrtw2r_odt_on;
+	xrtr2w = ac_tim->xrtr2w_odt_on;
+	tfaw = ac_tim->tfaw_4266;
+	tfaw_05t = ac_tim->tfaw_4266_05T;
+	trrd = ac_tim->trrd_4266;
+	trrd_05t = ac_tim->trrd_4266_05T;
+	xtrtrt = ac_tim->xrtr2r_new_mode;
+	xrtwtw = ac_tim->xrtw2w_new_mode;
+	tmrr2w = ac_tim->tmrr2w_odt_on;
+
+	if (READ32_BITFIELD(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl,
+			    SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN))
+		datlat_dsel = ac_tim->datlat;
+	else
+		datlat_dsel = ac_tim->datlat > 1 ? ac_tim->datlat - 1 : 0;
+
+	if (ac_tim->dqsinctl >= 2) {
+		rank_inctl_root = ac_tim->dqsinctl - 2;
+	} else {
+		dramc_err("rank_inctl_root <2, need check\n");
+		rank_inctl_root = 0;
+	}
+	phs_inctl = (ac_tim->dqsinctl == 0) ? 0 : (ac_tim->dqsinctl - 1);
+
+	if (freq_group <= DDRFREQ_800) {
+		if (get_div_mode(cali) == DIV4_MODE)	{
+			tx_rank_inctl = 1;
+			tx_dly = 2;
+		} else {
+			tx_rank_inctl = 0;
+			tx_dly = 1;
+		}
+	} else {
+		tx_rank_inctl = 1;
+		tx_dly = 2;
+	}
+
+	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+		SET32_BITFIELDS(&ch[chn].ao.shu_actim1,
+			SHU_ACTIM1_TRAS, ac_tim->tras,
+			SHU_ACTIM1_TRP, ac_tim->trp,
+			SHU_ACTIM1_TRPAB, ac_tim->trpab,
+			SHU_ACTIM1_TMRWCKEL, ac_tim->tmrwckel,
+			SHU_ACTIM1_TRC, ac_tim->trc);
+		SET32_BITFIELDS(&ch[chn].ao.shu_actim3,
+			SHU_ACTIM3_TRFC, ac_tim->trfc,
+			SHU_ACTIM3_TR2MRR, ac_tim->tr2mrr,
+			SHU_ACTIM3_TRFCPB, ac_tim->trfcpb);
+		SET32_BITFIELDS(&ch[chn].ao.shu_actim2,
+			SHU_ACTIM2_TXP, ac_tim->txp,
+			SHU_ACTIM2_TMRRI, ac_tim->tmrri,
+			SHU_ACTIM2_TFAW, tfaw,
+			SHU_ACTIM2_TR2W, trtw,
+			SHU_ACTIM2_TRTP, ac_tim->trtp);
+		SET32_BITFIELDS(&ch[chn].ao.shu_actim0,
+			SHU_ACTIM0_TRCD, ac_tim->trcd,
+			SHU_ACTIM0_TWR, ac_tim->twr,
+			SHU_ACTIM0_TRRD, trrd);
+		SET32_BITFIELDS(&ch[chn].ao.shu_actim5,
+			SHU_ACTIM5_TPBR2PBR, ac_tim->tpbr2pbr,
+			SHU_ACTIM5_TWTPD, ac_tim->twtpd,
+			SHU_ACTIM5_TPBR2ACT, ac_tim->tpbr2act);
+		SET32_BITFIELDS(&ch[chn].ao.shu_actim6,
+			SHU_ACTIM6_TR2MRW, ac_tim->tr2mrw,
+			SHU_ACTIM6_TW2MRW, ac_tim->tw2mrw,
+			SHU_ACTIM6_TMRD, ac_tim->tmrd,
+			SHU_ACTIM6_TZQLAT2, ac_tim->zqlat2,
+			SHU_ACTIM6_TMRW, ac_tim->tmrw);
+		SET32_BITFIELDS(&ch[chn].ao.shu_actim4,
+			SHU_ACTIM4_TMRR2MRW, ac_tim->tmrr2mrw,
+			SHU_ACTIM4_TMRR2W, tmrr2w,
+			SHU_ACTIM4_TZQCS, ac_tim->tzqcs,
+			SHU_ACTIM4_TXREFCNT, ac_tim->txrefcnt);
+		SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl, SHU_CKECTRL_TCKEPRD, ac_tim->ckeprd);
+		SET32_BITFIELDS(&ch[chn].ao.shu_actim_xrt,
+			SHU_ACTIM_XRT_XRTW2W, xrtwtw,
+			SHU_ACTIM_XRT_XRTW2R, xrtw2r,
+			SHU_ACTIM_XRT_XRTR2W, xrtr2w,
+			SHU_ACTIM_XRT_XRTR2R, xtrtrt);
+		SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg,
+			SHU_HWSET_VRCG_VRCGDIS_PRDCNT, ac_tim->vrcgdis_prdcnt);
+		SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr2,
+			SHU_HWSET_MR2_HWSET_MR2_OP, ac_tim->hwset_mr2_op);
+		SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr13,
+			SHU_HWSET_MR13_HWSET_MR13_OP, ac_tim->hwset_mr13_op);
+		SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t,
+			SHU_AC_TIME_05T_TWTR_M05T, ac_tim->twtr_05T,
+			SHU_AC_TIME_05T_TR2W_05T, trtw_05t,
+			SHU_AC_TIME_05T_TWTPD_M05T, ac_tim->twtpd_05T,
+			SHU_AC_TIME_05T_TFAW_05T, tfaw_05t,
+			SHU_AC_TIME_05T_TRRD_05T, trrd_05t,
+			SHU_AC_TIME_05T_TWR_M05T, ac_tim->twr_05T,
+			SHU_AC_TIME_05T_TRAS_05T, ac_tim->tras_05T,
+			SHU_AC_TIME_05T_TRPAB_05T, ac_tim->trpab_05T,
+			SHU_AC_TIME_05T_TRP_05T, ac_tim->trp_05T,
+			SHU_AC_TIME_05T_TRCD_05T, ac_tim->trcd_05T,
+			SHU_AC_TIME_05T_TRTP_05T, ac_tim->trtp_05T,
+			SHU_AC_TIME_05T_TXP_05T, ac_tim->txp_05T);
+		SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t,
+			SHU_AC_TIME_05T_TRFC_05T, ac_tim->trfc_05T,
+			SHU_AC_TIME_05T_TRFCPB_05T, ac_tim->trfcpb_05T,
+			SHU_AC_TIME_05T_TPBR2PBR_05T, ac_tim->tpbr2pbr_05T,
+			SHU_AC_TIME_05T_TPBR2ACT_05T, ac_tim->tpbr2act_05T,
+			SHU_AC_TIME_05T_TR2MRW_05T, ac_tim->tr2mrw_05T,
+			SHU_AC_TIME_05T_TW2MRW_05T, ac_tim->tw2mrw_05T,
+			SHU_AC_TIME_05T_TMRR2MRW_05T, ac_tim->tmrr2mrw_05T,
+			SHU_AC_TIME_05T_TMRW_05T, ac_tim->tmrw_05T,
+			SHU_AC_TIME_05T_TMRD_05T, ac_tim->tmrd_05T,
+			SHU_AC_TIME_05T_TMRWCKEL_05T, ac_tim->tmrwckel_05T,
+			SHU_AC_TIME_05T_TMRRI_05T, ac_tim->tmrri_05T,
+			SHU_AC_TIME_05T_TRC_05T, ac_tim->trc_05T);
+		SET32_BITFIELDS(&ch[chn].ao.shu_actim0, SHU_ACTIM0_TWTR, ac_tim->twtr);
+		SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl,
+			SHU_CKECTRL_TPDE, ac_tim->tpde,
+			SHU_CKECTRL_TPDX, ac_tim->tpdx,
+			SHU_CKECTRL_TPDE_05T, ac_tim->tpde_05T,
+			SHU_CKECTRL_TPDX_05T, ac_tim->tpdx_05T);
+		SET32_BITFIELDS(&ch[chn].ao.shu_actim5, SHU_ACTIM5_TR2PD, ac_tim->trtpd);
+		SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t,
+			SHU_AC_TIME_05T_TR2PD_05T, ac_tim->trtpd_05T);
+		SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0,
+			SHU_AC_DERATING0_TRCD_DERATE, ac_tim->trcd_derate,
+			SHU_AC_DERATING0_TRRD_DERATE, ac_tim->trrd_derate);
+		SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating1,
+			SHU_AC_DERATING1_TRC_DERATE, ac_tim->trc_derate,
+			SHU_AC_DERATING1_TRAS_DERATE, ac_tim->tras_derate,
+			SHU_AC_DERATING1_TRP_DERATE, ac_tim->trp_derate,
+			SHU_AC_DERATING1_TRPAB_DERATE, ac_tim->trpab_derate);
+		SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating_05t,
+			SHU_AC_DERATING_05T_TRRD_05T_DERATE, ac_tim->trrd_derate_05T,
+			SHU_AC_DERATING_05T_TRAS_05T_DERATE, ac_tim->tras_derate_05T,
+			SHU_AC_DERATING_05T_TRPAB_05T_DERATE, ac_tim->trpab_derate_05T,
+			SHU_AC_DERATING_05T_TRP_05T_DERATE, ac_tim->trp_derate_05T,
+			SHU_AC_DERATING_05T_TRCD_05T_DERATE, ac_tim->trcd_derate_05T,
+			SHU_AC_DERATING_05T_TRC_05T_DERATE, ac_tim->trc_derate_05T);
+		SET32_BITFIELDS(&ch[chn].ao.refctrl3, REFCTRL3_REF_DERATING_EN, 0xc0);
+		SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0,
+			SHU_AC_DERATING0_ACDERATEEN, 0x1);
+		SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[0].misc_shu_rk_dqsctl,
+			MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim->dqsinctl);
+		SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[1].misc_shu_rk_dqsctl,
+			MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim->dqsinctl);
+		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_odtctrl,
+			MISC_SHU_ODTCTRL_RODT_LAT, ac_tim->dqsinctl);
+		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl,
+			MISC_SHU_RANKCTL_RANKINCTL_PHY, ac_tim->dqsinctl,
+			MISC_SHU_RANKCTL_RANKINCTL_ROOT1, rank_inctl_root,
+			MISC_SHU_RANKCTL_RANKINCTL, rank_inctl_root);
+		SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rank_sel_stb,
+			SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, phs_inctl);
+		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rdat,
+			MISC_SHU_RDAT_DATLAT, ac_tim->datlat,
+			MISC_SHU_RDAT_DATLAT_DSEL, datlat_dsel,
+			MISC_SHU_RDAT_DATLAT_DSEL_PHY, datlat_dsel);
+		SET32_BITFIELDS(&ch[chn].ao.shu_actiming_conf,
+			SHU_ACTIMING_CONF_REFBW_FR, tref_bw);
+		rank_inctl = READ32_BITFIELD(&ch[0].phy_ao.misc_shu_rankctl,
+			MISC_SHU_RANKCTL_RANKINCTL);
+		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl,
+			MISC_SHU_RANKCTL_RANKINCTL_RXDLY, rank_inctl);
+		SET32_BITFIELDS(&ch[chn].ao.shu_tx_rankctl,
+			SHU_TX_RANKCTL_TXRANKINCTL_ROOT, root,
+			SHU_TX_RANKCTL_TXRANKINCTL, tx_rank_inctl,
+			SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, tx_dly);
+	}
+}
+
 static void set_cke2rank_independent(void)
 {
 	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
@@ -4126,6 +4328,8 @@ static void dramc_init(const struct ddr_cali *cali)
 	dramc_8_phase_cal(cali);
 	dramc_duty_calibration(cali->params);
 	dramc_mode_reg_init(cali);
+
+	ddr_update_ac_timing(cali);
 }
 
 static void dramc_before_calibration(const struct ddr_cali *cali)
diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c
index 8eba016dd8..0373c8212c 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_main.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_main.c
@@ -6,6 +6,186 @@
 #include <soc/pll_common.h>
 #include <soc/regulator.h>
 
+static void dramc_ac_timing_optimize(const struct ddr_cali *cali)
+{
+	u8 rf_group, cab_id;
+	u8 trfc, trfc_05t, trfc_pb, trfrc_pb05t, tx_ref_cnt;
+
+	enum {
+		TRFCAB_130,
+		TRFCAB_180,
+		TRFCAB_280,
+		TRFCAB_380,
+		TRFCAB_NUM,
+	};
+	enum {
+		GRP_DDR800_DIV4_ACTIM,
+		GRP_DDR1200_ACTIM,
+		GRP_DDR1600_ACTIM,
+		GRP_DDR1866_ACTIM,
+		GRP_DDR2400_ACTIM,
+		GRP_DDR3200_ACTIM,
+		GRP_DDR4266_ACTIM,
+		GRP_ACTIM_NUM,
+	};
+	struct optimize_ac_time {
+		u8 trfc;
+		u8 trfc_05t;
+		u8 trfc_pb;
+		u8 trfrc_pb05t;
+		u16 tx_ref_cnt;
+	};
+
+	const u8 density = cali->density;
+	const dram_freq_grp freq_group = get_freq_group(cali);
+
+	/* tRFCab */
+	struct optimize_ac_time *ptr_trfcab_opt;
+	struct optimize_ac_time trfcab_opt[GRP_ACTIM_NUM][TRFCAB_NUM] = {
+		[GRP_DDR800_DIV4_ACTIM] = {
+			{.trfc = 14, .trfc_05t = 0, .trfc_pb = 0,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 28},
+			{.trfc = 24, .trfc_05t = 0, .trfc_pb = 6,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 38},
+			{.trfc = 44, .trfc_05t = 0, .trfc_pb = 16,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 58},
+			{.trfc = 64, .trfc_05t = 0, .trfc_pb = 26,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 78}
+		},
+		[GRP_DDR1200_ACTIM] = {
+			{.trfc = 8, .trfc_05t = 0, .trfc_pb = 0,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 21},
+			{.trfc = 15, .trfc_05t = 1, .trfc_pb = 2,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 29},
+			{.trfc = 30, .trfc_05t = 1, .trfc_pb = 9,
+				.trfrc_pb05t = 1, .tx_ref_cnt = 44},
+			{.trfc = 45, .trfc_05t = 1, .trfc_pb = 17,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 59}
+		},
+		[GRP_DDR1600_ACTIM] = {
+			{.trfc = 14, .trfc_05t = 0, .trfc_pb = 0,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 28},
+			{.trfc = 24, .trfc_05t = 0, .trfc_pb = 6,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 38},
+			{.trfc = 44, .trfc_05t = 0, .trfc_pb = 16,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 58},
+			{.trfc = 64, .trfc_05t = 0, .trfc_pb = 26,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 78}
+		},
+		[GRP_DDR1866_ACTIM] = {
+			{.trfc = 18, .trfc_05t = 1, .trfc_pb = 2,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 33},
+			{.trfc = 30, .trfc_05t = 0, .trfc_pb = 9,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 44},
+			{.trfc = 53, .trfc_05t = 1, .trfc_pb = 21,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 68},
+			{.trfc = 77, .trfc_05t = 0, .trfc_pb = 32,
+				.trfrc_pb05t = 1, .tx_ref_cnt = 91}
+		},
+		[GRP_DDR2400_ACTIM] = {
+			{.trfc = 27, .trfc_05t = 1, .trfc_pb = 6,
+				.trfrc_pb05t = 1, .tx_ref_cnt = 42},
+			{.trfc = 42, .trfc_05t = 1, .trfc_pb = 15,
+				.trfrc_pb05t = 1, .tx_ref_cnt = 57},
+			{.trfc = 72, .trfc_05t = 1, .trfc_pb = 30,
+				.trfrc_pb05t = 1, .tx_ref_cnt = 87},
+			{.trfc = 102, .trfc_05t = 1, .trfc_pb = 45,
+				.trfrc_pb05t = 1, .tx_ref_cnt = 117}
+		},
+		[GRP_DDR3200_ACTIM] = {
+			{.trfc = 40, .trfc_05t = 0, .trfc_pb = 12,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 55},
+			{.trfc = 60, .trfc_05t = 0, .trfc_pb = 24,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 75},
+			{.trfc = 100, .trfc_05t = 0, .trfc_pb = 44,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 115},
+			{.trfc = 140, .trfc_05t = 0, .trfc_pb = 64,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 155}
+		},
+		[GRP_DDR4266_ACTIM] = {
+			{.trfc = 57, .trfc_05t = 1, .trfc_pb = 20,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 74},
+			{.trfc = 84, .trfc_05t = 0, .trfc_pb = 36,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 100},
+			{.trfc = 137, .trfc_05t = 1, .trfc_pb = 63,
+				.trfrc_pb05t = 0, .tx_ref_cnt = 154},
+			{.trfc = 191, .trfc_05t = 0, .trfc_pb = 89,
+				.trfrc_pb05t = 1, .tx_ref_cnt = 207}
+		}
+	};
+
+	switch (density) {
+	case 0x0:
+		rf_group = TRFCAB_130;
+		break;
+	case 0x1:
+	case 0x2:
+		rf_group = TRFCAB_180;
+		break;
+	case 0x3:
+	case 0x4:
+		rf_group = TRFCAB_280;
+		break;
+	case 0x5:
+	case 0x6:
+		rf_group = TRFCAB_380;
+		break;
+	default:
+		die("Invalid DDR density %u\n", density);
+		return;
+	}
+
+	switch (freq_group) {
+	case DDRFREQ_400:
+		cab_id = GRP_DDR800_DIV4_ACTIM;
+		break;
+	case DDRFREQ_600:
+		cab_id = GRP_DDR1200_ACTIM;
+		break;
+	case DDRFREQ_800:
+		cab_id = GRP_DDR1600_ACTIM;
+		break;
+	case DDRFREQ_933:
+		cab_id = GRP_DDR1866_ACTIM;
+		break;
+	case DDRFREQ_1200:
+		cab_id = GRP_DDR2400_ACTIM;
+		break;
+	case DDRFREQ_1600:
+		cab_id = GRP_DDR3200_ACTIM;
+		break;
+	case DDRFREQ_2133:
+		cab_id = GRP_DDR4266_ACTIM;
+		break;
+	default:
+		die("Invalid DDR frequency group %u\n", freq_group);
+		return;
+	}
+
+	ptr_trfcab_opt = &trfcab_opt[cab_id][0];
+	trfc = ptr_trfcab_opt[rf_group].trfc;
+	trfc_05t = ptr_trfcab_opt[rf_group].trfc_05t;
+	trfc_pb = ptr_trfcab_opt[rf_group].trfc_pb;
+	trfrc_pb05t = ptr_trfcab_opt[rf_group].trfrc_pb05t;
+	tx_ref_cnt = ptr_trfcab_opt[rf_group].tx_ref_cnt;
+
+	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+		SET32_BITFIELDS(&ch[chn].ao.shu_actim3,
+				SHU_ACTIM3_TRFC, trfc);
+		SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t,
+				SHU_AC_TIME_05T_TRFC_05T, trfc_05t);
+		SET32_BITFIELDS(&ch[chn].ao.shu_actim4,
+				SHU_ACTIM4_TXREFCNT, tx_ref_cnt);
+		SET32_BITFIELDS(&ch[chn].ao.shu_actim3,
+				SHU_ACTIM3_TRFCPB, trfc_pb);
+		SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t,
+				SHU_AC_TIME_05T_TRFCPB_05T, trfrc_pb05t);
+		dramc_dbg("Density (MR8 OP[5:2]) %u, TRFC %u, TRFC_05T %u, TXREFCNT %u, "
+			  "TRFCpb %u, TRFCpb_05T %u\n",
+			  density, trfc, trfc_05t, tx_ref_cnt, trfc_pb, trfrc_pb05t);
+	}
+}
+
 static void set_vcore_voltage(const struct ddr_cali *cali)
 {
 	u32 vcore = get_vcore_value(cali);
@@ -140,6 +320,8 @@ void init_dram(const struct dramc_data *dparam)
 		if (first_freq_k)
 			get_dram_info_after_cal(&cali);
 
+		dramc_ac_timing_optimize(&cali);
+
 		first_freq_k = false;
 	}
 }
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h b/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h
new file mode 100644
index 0000000000..f00101a3a9
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h
@@ -0,0 +1,972 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__
+#define __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__
+
+#include <stdint.h>
+#include <sys/types.h>
+#include <soc/dramc_common_mt8192.h>
+#include <soc/dramc_pi_api.h>
+
+/* Normal Mode and Byte Mode */
+#define AC_TIMING_NUMBER	(DDRFREQ_MAX * 2)
+
+struct ac_timing {
+	u8 cbt_mode, read_dbi;
+	u8 div_mode;
+	u16 freq_group;
+	u16 read_lat, write_lat;
+	u16 dqsinctl, datlat;
+	u16 tras;
+	u16 trp;
+	u16 trpab;
+	u16 trc;
+	u16 trfc;
+	u16 trfcpb;
+	u16 txp;
+	u16 trtp;
+	u16 trcd;
+	u16 twr;
+	u16 twtr;
+	u16 tpbr2pbr;
+	u16 tpbr2act;
+	u16 tr2mrw;
+	u16 tw2mrw;
+	u16 tmrr2mrw;
+	u16 tmrw;
+	u16 tmrd;
+	u16 tmrwckel;
+	u16 tpde;
+	u16 tpdx;
+	u16 tmrri;
+	u16 trrd;
+	u16 trrd_4266;
+	u16 tfaw;
+	u16 tfaw_4266;
+	u16 trtw_odt_off;
+	u16 trtw_odt_on;
+	u16 txrefcnt;
+	u16 tzqcs;
+	u16 xrtw2w_new_mode;
+	u16 xrtw2w_old_mode;
+	u16 xrtw2r_odt_on;
+	u16 xrtw2r_odt_off;
+	u16 xrtr2w_odt_on;
+	u16 xrtr2w_odt_off;
+	u16 xrtr2r_new_mode;
+	u16 xrtr2r_old_mode;
+	u16 tr2mrr;
+	u16 vrcgdis_prdcnt;
+	u16 hwset_mr2_op;
+	u16 hwset_mr13_op;
+	u16 hwset_vrcg_op;
+	u16 trcd_derate;
+	u16 trc_derate;
+	u16 tras_derate;
+	u16 trpab_derate;
+	u16 trp_derate;
+	u16 trrd_derate;
+	u16 trtpd;
+	u16 twtpd;
+	u16 tmrr2w_odt_off;
+	u16 tmrr2w_odt_on;
+	u16 ckeprd;
+	u16 ckelckcnt;
+	u16 zqlat2;
+	u16 tras_05T;
+	u16 trp_05T;
+	u16 trpab_05T;
+	u16 trc_05T;
+	u16 trfc_05T;
+	u16 trfcpb_05T;
+	u16 txp_05T;
+	u16 trtp_05T;
+	u16 trcd_05T;
+	u16 twr_05T;
+	u16 twtr_05T;
+	u16 tpbr2pbr_05T;
+	u16 tpbr2act_05T;
+	u16 tr2mrw_05T;
+	u16 tw2mrw_05T;
+	u16 tmrr2mrw_05T;
+	u16 tmrw_05T;
+	u16 tmrd_05T;
+	u16 tmrwckel_05T;
+	u16 tpde_05T;
+	u16 tpdx_05T;
+	u16 tmrri_05T;
+	u16 trrd_05T;
+	u16 trrd_4266_05T;
+	u16 tfaw_05T;
+	u16 tfaw_4266_05T;
+	u16 trtw_odt_off_05T;
+	u16 trtw_odt_on_05T;
+	u16 trcd_derate_05T;
+	u16 trc_derate_05T;
+	u16 tras_derate_05T;
+	u16 trpab_derate_05T;
+	u16 trp_derate_05T;
+	u16 trrd_derate_05T;
+	u16 trtpd_05T;
+	u16 twtpd_05T;
+};
+
+/* Normal Mode and Byte Mode for each frequency */
+static const struct ac_timing ac_timing_tbl[AC_TIMING_NUMBER] = {
+	{
+		.freq_group = DDRFREQ_2133, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 36, .write_lat =  18, .div_mode =  DIV8_MODE,
+		.tras = 14, .tras_05T = 0,
+		.trp = 8, .trp_05T = 1,
+		.trpab = 10, .trpab_05T = 0,
+		.trc = 23, .trc_05T = 0,
+		.trfc = 137, .trfc_05T = 1,
+		.trfcpb = 63, .trfcpb_05T = 0,
+		.txp = 1, .txp_05T = 0,
+		.trtp = 2, .trtp_05T = 1,
+		.trcd = 10, .trcd_05T = 0,
+		.twr = 15, .twr_05T = 0,
+		.twtr = 10, .twtr_05T = 1,
+		.tpbr2pbr = 41, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 17, .tr2mrw_05T = 0,
+		.tw2mrw = 11, .tw2mrw_05T = 0,
+		.tmrr2mrw = 14, .tmrr2mrw_05T = 0,
+		.tmrw = 6, .tmrw_05T = 0,
+		.tmrd = 8, .tmrd_05T = 0,
+		.tmrwckel = 9, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 14, .tmrri_05T = 0,
+		.trrd = 4, .trrd_05T = 1,
+		.trrd_4266 = 3, .trrd_4266_05T = 0,
+		.tfaw = 13, .tfaw_05T = 1,
+		.tfaw_4266 = 8, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 6, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 8, .trtw_odt_on_05T = 0,
+		.txrefcnt = 154,
+		.tzqcs = 46,
+		.xrtw2w_new_mode = 5,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 1,
+		.xrtw2r_odt_off = 1,
+		.xrtr2w_odt_on = 7,
+		.xrtr2w_odt_off = 7,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 7,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 54,
+		.hwset_mr2_op = 63,
+		.hwset_mr13_op = 216,
+		.hwset_vrcg_op = 208,
+		.trcd_derate = 11, .trcd_derate_05T = 0,
+		.trc_derate = 26, .trc_derate_05T = 0,
+		.tras_derate = 15, .tras_derate_05T = 0,
+		.trpab_derate = 11, .trpab_derate_05T = 0,
+		.trp_derate = 9, .trp_derate_05T = 1,
+		.trrd_derate = 5, .trrd_derate_05T = 1,
+		.trtpd = 14, .trtpd_05T = 1,
+		.twtpd = 18, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 10,
+		.tmrr2w_odt_on = 12,
+		.ckeprd = 3,
+		.ckelckcnt = 3,
+		.zqlat2 = 16,
+		.dqsinctl = 7, .datlat = 18
+	},
+	{
+		.freq_group = DDRFREQ_2133, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 40, .write_lat =  18, .div_mode =  DIV8_MODE,
+		.tras = 14, .tras_05T = 0,
+		.trp = 8, .trp_05T = 1,
+		.trpab = 10, .trpab_05T = 0,
+		.trc = 23, .trc_05T = 0,
+		.trfc = 137, .trfc_05T = 1,
+		.trfcpb = 63, .trfcpb_05T = 0,
+		.txp = 1, .txp_05T = 0,
+		.trtp = 2, .trtp_05T = 1,
+		.trcd = 10, .trcd_05T = 0,
+		.twr = 16, .twr_05T = 0,
+		.twtr = 11, .twtr_05T = 1,
+		.tpbr2pbr = 41, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 18, .tr2mrw_05T = 0,
+		.tw2mrw = 11, .tw2mrw_05T = 0,
+		.tmrr2mrw = 15, .tmrr2mrw_05T = 0,
+		.tmrw = 6, .tmrw_05T = 0,
+		.tmrd = 8, .tmrd_05T = 0,
+		.tmrwckel = 9, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 14, .tmrri_05T = 0,
+		.trrd = 4, .trrd_05T = 1,
+		.trrd_4266 = 3, .trrd_4266_05T = 0,
+		.tfaw = 13, .tfaw_05T = 1,
+		.tfaw_4266 = 8, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 7, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 9, .trtw_odt_on_05T = 0,
+		.txrefcnt = 154,
+		.tzqcs = 46,
+		.xrtw2w_new_mode = 5,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 1,
+		.xrtw2r_odt_off = 1,
+		.xrtr2w_odt_on = 8,
+		.xrtr2w_odt_off = 8,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 7,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 54,
+		.hwset_mr2_op = 63,
+		.hwset_mr13_op = 216,
+		.hwset_vrcg_op = 208,
+		.trcd_derate = 11, .trcd_derate_05T = 0,
+		.trc_derate = 26, .trc_derate_05T = 0,
+		.tras_derate = 15, .tras_derate_05T = 0,
+		.trpab_derate = 11, .trpab_derate_05T = 0,
+		.trp_derate = 9, .trp_derate_05T = 1,
+		.trrd_derate = 5, .trrd_derate_05T = 1,
+		.trtpd = 15, .trtpd_05T = 1,
+		.twtpd = 19, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 11,
+		.tmrr2w_odt_on = 13,
+		.ckeprd = 3,
+		.ckelckcnt = 3,
+		.zqlat2 = 16,
+		.dqsinctl = 7, .datlat = 18
+	},
+	{
+		.freq_group = DDRFREQ_1600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 28, .write_lat =  14, .div_mode =  DIV8_MODE,
+		.tras = 8, .tras_05T = 1,
+		.trp = 6, .trp_05T = 0,
+		.trpab = 7, .trpab_05T = 0,
+		.trc = 15, .trc_05T = 0,
+		.trfc = 100, .trfc_05T = 0,
+		.trfcpb = 44, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 1, .trtp_05T = 1,
+		.trcd = 7, .trcd_05T = 1,
+		.twr = 12, .twr_05T = 1,
+		.twtr = 7, .twtr_05T = 0,
+		.tpbr2pbr = 29, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 13, .tr2mrw_05T = 1,
+		.tw2mrw = 9, .tw2mrw_05T = 0,
+		.tmrr2mrw = 11, .tmrr2mrw_05T = 1,
+		.tmrw = 4, .tmrw_05T = 1,
+		.tmrd = 6, .tmrd_05T = 1,
+		.tmrwckel = 7, .tmrwckel_05T = 1,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 10, .tmrri_05T = 1,
+		.trrd = 3, .trrd_05T = 0,
+		.trrd_4266 = 2, .trrd_4266_05T = 0,
+		.tfaw = 8, .tfaw_05T = 0,
+		.tfaw_4266 = 4, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 4, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 6, .trtw_odt_on_05T = 0,
+		.txrefcnt = 115,
+		.tzqcs = 34,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 1,
+		.xrtw2r_odt_off = 1,
+		.xrtr2w_odt_on = 5,
+		.xrtr2w_odt_off = 5,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 7,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 40,
+		.hwset_mr2_op = 45,
+		.hwset_mr13_op = 216,
+		.hwset_vrcg_op = 208,
+		.trcd_derate = 8, .trcd_derate_05T = 0,
+		.trc_derate = 17, .trc_derate_05T = 0,
+		.tras_derate = 9, .tras_derate_05T = 1,
+		.trpab_derate = 8, .trpab_derate_05T = 0,
+		.trp_derate = 6, .trp_derate_05T = 1,
+		.trrd_derate = 4, .trrd_derate_05T = 0,
+		.trtpd = 12, .trtpd_05T = 0,
+		.twtpd = 14, .twtpd_05T = 1,
+		.tmrr2w_odt_off = 8,
+		.tmrr2w_odt_on = 10,
+		.ckeprd = 2,
+		.ckelckcnt = 2,
+		.zqlat2 = 12,
+		.dqsinctl = 5, .datlat = 15
+	},
+	{
+		.freq_group = DDRFREQ_1600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 32, .write_lat =  14, .div_mode =  DIV8_MODE,
+		.tras = 8, .tras_05T = 1,
+		.trp = 6, .trp_05T = 0,
+		.trpab = 7, .trpab_05T = 0,
+		.trc = 15, .trc_05T = 0,
+		.trfc = 100, .trfc_05T = 0,
+		.trfcpb = 44, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 1, .trtp_05T = 1,
+		.trcd = 7, .trcd_05T = 1,
+		.twr = 12, .twr_05T = 1,
+		.twtr = 8, .twtr_05T = 0,
+		.tpbr2pbr = 29, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 14, .tr2mrw_05T = 1,
+		.tw2mrw = 9, .tw2mrw_05T = 0,
+		.tmrr2mrw = 12, .tmrr2mrw_05T = 1,
+		.tmrw = 4, .tmrw_05T = 1,
+		.tmrd = 6, .tmrd_05T = 1,
+		.tmrwckel = 7, .tmrwckel_05T = 1,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 10, .tmrri_05T = 1,
+		.trrd = 3, .trrd_05T = 0,
+		.trrd_4266 = 2, .trrd_4266_05T = 0,
+		.tfaw = 8, .tfaw_05T = 0,
+		.tfaw_4266 = 4, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 5, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 7, .trtw_odt_on_05T = 0,
+		.txrefcnt = 115,
+		.tzqcs = 34,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 1,
+		.xrtw2r_odt_off = 1,
+		.xrtr2w_odt_on = 6,
+		.xrtr2w_odt_off = 6,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 7,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 40,
+		.hwset_mr2_op = 45,
+		.hwset_mr13_op = 216,
+		.hwset_vrcg_op = 208,
+		.trcd_derate = 8, .trcd_derate_05T = 0,
+		.trc_derate = 17, .trc_derate_05T = 0,
+		.tras_derate = 9, .tras_derate_05T = 1,
+		.trpab_derate = 8, .trpab_derate_05T = 0,
+		.trp_derate = 6, .trp_derate_05T = 1,
+		.trrd_derate = 4, .trrd_derate_05T = 0,
+		.trtpd = 13, .trtpd_05T = 0,
+		.twtpd = 15, .twtpd_05T = 1,
+		.tmrr2w_odt_off = 9,
+		.tmrr2w_odt_on = 11,
+		.ckeprd = 2,
+		.ckelckcnt = 2,
+		.zqlat2 = 12,
+		.dqsinctl = 5, .datlat = 15
+	},
+	{
+		.freq_group = DDRFREQ_1200, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 24, .write_lat =  12, .div_mode =  DIV8_MODE,
+		.tras = 4, .tras_05T = 1,
+		.trp = 4, .trp_05T = 0,
+		.trpab = 5, .trpab_05T = 0,
+		.trc = 9, .trc_05T = 1,
+		.trfc = 72, .trfc_05T = 1,
+		.trfcpb = 30, .trfcpb_05T = 1,
+		.txp = 0, .txp_05T = 1,
+		.trtp = 1, .trtp_05T = 0,
+		.trcd = 5, .trcd_05T = 1,
+		.twr = 9, .twr_05T = 1,
+		.twtr = 6, .twtr_05T = 1,
+		.tpbr2pbr = 20, .tpbr2pbr_05T = 1,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 12, .tr2mrw_05T = 0,
+		.tw2mrw = 8, .tw2mrw_05T = 0,
+		.tmrr2mrw = 10, .tmrr2mrw_05T = 0,
+		.tmrw = 4, .tmrw_05T = 0,
+		.tmrd = 5, .tmrd_05T = 0,
+		.tmrwckel = 6, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 8, .tmrri_05T = 0,
+		.trrd = 2, .trrd_05T = 1,
+		.trrd_4266 = 1, .trrd_4266_05T = 1,
+		.tfaw = 4, .tfaw_05T = 1,
+		.tfaw_4266 = 1, .tfaw_4266_05T = 1,
+		.trtw_odt_off = 3, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 6, .trtw_odt_on_05T = 0,
+		.txrefcnt = 87,
+		.tzqcs = 26,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 2,
+		.xrtw2r_odt_off = 2,
+		.xrtr2w_odt_on = 5,
+		.xrtr2w_odt_off = 5,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 31,
+		.hwset_mr2_op = 36,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 6, .trcd_derate_05T = 0,
+		.trc_derate = 10, .trc_derate_05T = 1,
+		.tras_derate = 5, .tras_derate_05T = 0,
+		.trpab_derate = 5, .trpab_derate_05T = 1,
+		.trp_derate = 4, .trp_derate_05T = 1,
+		.trrd_derate = 3, .trrd_derate_05T = 0,
+		.trtpd = 10, .trtpd_05T = 1,
+		.twtpd = 12, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 6,
+		.tmrr2w_odt_on = 8,
+		.ckeprd = 2,
+		.ckelckcnt = 2,
+		.zqlat2 = 10,
+		.dqsinctl = 4, .datlat = 13
+	},
+	{
+		.freq_group = DDRFREQ_1200, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 26, .write_lat =  12, .div_mode =  DIV8_MODE,
+		.tras = 4, .tras_05T = 1,
+		.trp = 4, .trp_05T = 0,
+		.trpab = 5, .trpab_05T = 0,
+		.trc = 9, .trc_05T = 1,
+		.trfc = 72, .trfc_05T = 1,
+		.trfcpb = 30, .trfcpb_05T = 1,
+		.txp = 0, .txp_05T = 1,
+		.trtp = 1, .trtp_05T = 0,
+		.trcd = 5, .trcd_05T = 1,
+		.twr = 10, .twr_05T = 0,
+		.twtr = 6, .twtr_05T = 0,
+		.tpbr2pbr = 20, .tpbr2pbr_05T = 1,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 12, .tr2mrw_05T = 1,
+		.tw2mrw = 8, .tw2mrw_05T = 0,
+		.tmrr2mrw = 10, .tmrr2mrw_05T = 1,
+		.tmrw = 4, .tmrw_05T = 0,
+		.tmrd = 5, .tmrd_05T = 0,
+		.tmrwckel = 6, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 8, .tmrri_05T = 0,
+		.trrd = 2, .trrd_05T = 1,
+		.trrd_4266 = 1, .trrd_4266_05T = 1,
+		.tfaw = 4, .tfaw_05T = 1,
+		.tfaw_4266 = 1, .tfaw_4266_05T = 1,
+		.trtw_odt_off = 4, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 6, .trtw_odt_on_05T = 0,
+		.txrefcnt = 87,
+		.tzqcs = 26,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 1,
+		.xrtw2r_odt_off = 1,
+		.xrtr2w_odt_on = 5,
+		.xrtr2w_odt_off = 5,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 31,
+		.hwset_mr2_op = 36,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 6, .trcd_derate_05T = 0,
+		.trc_derate = 10, .trc_derate_05T = 1,
+		.tras_derate = 5, .tras_derate_05T = 0,
+		.trpab_derate = 5, .trpab_derate_05T = 1,
+		.trp_derate = 4, .trp_derate_05T = 1,
+		.trrd_derate = 3, .trrd_derate_05T = 0,
+		.trtpd = 11, .trtpd_05T = 0,
+		.twtpd = 13, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 7,
+		.tmrr2w_odt_on = 9,
+		.ckeprd = 2,
+		.ckelckcnt = 2,
+		.zqlat2 = 10,
+		.dqsinctl = 4, .datlat = 13
+	},
+	{
+		.freq_group = DDRFREQ_933, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 20, .write_lat =  10, .div_mode =  DIV8_MODE,
+		.tras = 1, .tras_05T = 1,
+		.trp = 3, .trp_05T = 0,
+		.trpab = 3, .trpab_05T = 1,
+		.trc = 5, .trc_05T = 0,
+		.trfc = 53, .trfc_05T = 1,
+		.trfcpb = 21, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 0, .trtp_05T = 1,
+		.trcd = 4, .trcd_05T = 1,
+		.twr = 8, .twr_05T = 1,
+		.twtr = 5, .twtr_05T = 1,
+		.tpbr2pbr = 14, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 10, .tr2mrw_05T = 0,
+		.tw2mrw = 7, .tw2mrw_05T = 0,
+		.tmrr2mrw = 9, .tmrr2mrw_05T = 0,
+		.tmrw = 3, .tmrw_05T = 0,
+		.tmrd = 4, .tmrd_05T = 0,
+		.tmrwckel = 5, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 6, .tmrri_05T = 0,
+		.trrd = 1, .trrd_05T = 1,
+		.trrd_4266 = 1, .trrd_4266_05T = 0,
+		.tfaw = 1, .tfaw_05T = 1,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 3, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 5, .trtw_odt_on_05T = 0,
+		.txrefcnt = 68,
+		.tzqcs = 19,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 2,
+		.xrtw2r_odt_off = 2,
+		.xrtr2w_odt_on = 3,
+		.xrtr2w_odt_off = 3,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 24,
+		.hwset_mr2_op = 27,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 5, .trcd_derate_05T = 0,
+		.trc_derate = 6, .trc_derate_05T = 1,
+		.tras_derate = 2, .tras_derate_05T = 0,
+		.trpab_derate = 4, .trpab_derate_05T = 0,
+		.trp_derate = 3, .trp_derate_05T = 1,
+		.trrd_derate = 2, .trrd_derate_05T = 0,
+		.trtpd = 9, .trtpd_05T = 1,
+		.twtpd = 10, .twtpd_05T = 1,
+		.tmrr2w_odt_off = 5,
+		.tmrr2w_odt_on = 7,
+		.ckeprd = 1,
+		.ckelckcnt = 2,
+		.zqlat2 = 7,
+		.dqsinctl = 3, .datlat = 13
+	},
+	{
+		.freq_group = DDRFREQ_933, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 22, .write_lat =  10, .div_mode =  DIV8_MODE,
+		.tras = 1, .tras_05T = 1,
+		.trp = 3, .trp_05T = 0,
+		.trpab = 3, .trpab_05T = 1,
+		.trc = 5, .trc_05T = 0,
+		.trfc = 53, .trfc_05T = 1,
+		.trfcpb = 21, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 0, .trtp_05T = 1,
+		.trcd = 4, .trcd_05T = 1,
+		.twr = 8, .twr_05T = 0,
+		.twtr = 5, .twtr_05T = 0,
+		.tpbr2pbr = 14, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 10, .tr2mrw_05T = 1,
+		.tw2mrw = 7, .tw2mrw_05T = 0,
+		.tmrr2mrw = 9, .tmrr2mrw_05T = 1,
+		.tmrw = 3, .tmrw_05T = 0,
+		.tmrd = 4, .tmrd_05T = 0,
+		.tmrwckel = 5, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 6, .tmrri_05T = 0,
+		.trrd = 1, .trrd_05T = 1,
+		.trrd_4266 = 1, .trrd_4266_05T = 0,
+		.tfaw = 1, .tfaw_05T = 1,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 3, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 5, .trtw_odt_on_05T = 0,
+		.txrefcnt = 68,
+		.tzqcs = 19,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 2,
+		.xrtw2r_odt_off = 1,
+		.xrtr2w_odt_on = 4,
+		.xrtr2w_odt_off = 4,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 24,
+		.hwset_mr2_op = 27,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 5, .trcd_derate_05T = 0,
+		.trc_derate = 6, .trc_derate_05T = 1,
+		.tras_derate = 2, .tras_derate_05T = 0,
+		.trpab_derate = 4, .trpab_derate_05T = 0,
+		.trp_derate = 3, .trp_derate_05T = 1,
+		.trrd_derate = 2, .trrd_derate_05T = 0,
+		.trtpd = 10, .trtpd_05T = 0,
+		.twtpd = 11, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 6,
+		.tmrr2w_odt_on = 8,
+		.ckeprd = 1,
+		.ckelckcnt = 2,
+		.zqlat2 = 7,
+		.dqsinctl = 3, .datlat = 13
+	},
+	{
+		.freq_group = DDRFREQ_800, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 14, .write_lat =  8, .div_mode =  DIV8_MODE,
+		.tras = 0, .tras_05T = 0,
+		.trp = 2, .trp_05T = 1,
+		.trpab = 3, .trpab_05T = 0,
+		.trc = 3, .trc_05T = 0,
+		.trfc = 44, .trfc_05T = 0,
+		.trfcpb = 16, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 0, .trtp_05T = 1,
+		.trcd = 4, .trcd_05T = 0,
+		.twr = 7, .twr_05T = 1,
+		.twtr = 4, .twtr_05T = 1,
+		.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 8, .tr2mrw_05T = 1,
+		.tw2mrw = 6, .tw2mrw_05T = 1,
+		.tmrr2mrw = 7, .tmrr2mrw_05T = 0,
+		.tmrw = 3, .tmrw_05T = 0,
+		.tmrd = 3, .tmrd_05T = 1,
+		.tmrwckel = 4, .tmrwckel_05T = 1,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 5, .tmrri_05T = 1,
+		.trrd = 1, .trrd_05T = 0,
+		.trrd_4266 = 0, .trrd_4266_05T = 1,
+		.tfaw = 0, .tfaw_05T = 0,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 1, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 4, .trtw_odt_on_05T = 0,
+		.txrefcnt = 58,
+		.tzqcs = 16,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 3,
+		.xrtw2r_odt_off = 3,
+		.xrtr2w_odt_on = 3,
+		.xrtr2w_odt_off = 3,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 20,
+		.hwset_mr2_op = 18,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 4, .trcd_derate_05T = 0,
+		.trc_derate = 4, .trc_derate_05T = 0,
+		.tras_derate = 0, .tras_derate_05T = 1,
+		.trpab_derate = 3, .trpab_derate_05T = 1,
+		.trp_derate = 2, .trp_derate_05T = 1,
+		.trrd_derate = 1, .trrd_derate_05T = 1,
+		.trtpd = 7, .trtpd_05T = 1,
+		.twtpd = 9, .twtpd_05T = 1,
+		.tmrr2w_odt_off = 3,
+		.tmrr2w_odt_on = 5,
+		.ckeprd = 1,
+		.ckelckcnt = 2,
+		.zqlat2 = 6,
+		.dqsinctl = 2, .datlat = 10
+	},
+	{
+		.freq_group = DDRFREQ_800, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 16, .write_lat =  8, .div_mode =  DIV8_MODE,
+		.tras = 0, .tras_05T = 0,
+		.trp = 2, .trp_05T = 1,
+		.trpab = 3, .trpab_05T = 0,
+		.trc = 3, .trc_05T = 0,
+		.trfc = 44, .trfc_05T = 0,
+		.trfcpb = 16, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 0, .trtp_05T = 1,
+		.trcd = 4, .trcd_05T = 0,
+		.twr = 7, .twr_05T = 0,
+		.twtr = 4, .twtr_05T = 0,
+		.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 9, .tr2mrw_05T = 0,
+		.tw2mrw = 6, .tw2mrw_05T = 1,
+		.tmrr2mrw = 7, .tmrr2mrw_05T = 1,
+		.tmrw = 3, .tmrw_05T = 0,
+		.tmrd = 3, .tmrd_05T = 1,
+		.tmrwckel = 4, .tmrwckel_05T = 1,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 5, .tmrri_05T = 1,
+		.trrd = 1, .trrd_05T = 0,
+		.trrd_4266 = 0, .trrd_4266_05T = 1,
+		.tfaw = 0, .tfaw_05T = 0,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 2, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 4, .trtw_odt_on_05T = 0,
+		.txrefcnt = 58,
+		.tzqcs = 16,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 3,
+		.xrtw2r_odt_off = 2,
+		.xrtr2w_odt_on = 3,
+		.xrtr2w_odt_off = 3,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 20,
+		.hwset_mr2_op = 18,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 4, .trcd_derate_05T = 0,
+		.trc_derate = 4, .trc_derate_05T = 0,
+		.tras_derate = 0, .tras_derate_05T = 1,
+		.trpab_derate = 3, .trpab_derate_05T = 1,
+		.trp_derate = 2, .trp_derate_05T = 1,
+		.trrd_derate = 1, .trrd_derate_05T = 1,
+		.trtpd = 8, .trtpd_05T = 0,
+		.twtpd = 9, .twtpd_05T = 1,
+		.tmrr2w_odt_off = 4,
+		.tmrr2w_odt_on = 6,
+		.ckeprd = 1,
+		.ckelckcnt = 2,
+		.zqlat2 = 6,
+		.dqsinctl = 2, .datlat = 10
+	},
+	{
+		.freq_group = DDRFREQ_600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 14, .write_lat =  8, .div_mode =  DIV8_MODE,
+		.tras = 0, .tras_05T = 0,
+		.trp = 1, .trp_05T = 1,
+		.trpab = 2, .trpab_05T = 0,
+		.trc = 0, .trc_05T = 1,
+		.trfc = 30, .trfc_05T = 1,
+		.trfcpb = 9, .trfcpb_05T = 1,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 0, .trtp_05T = 1,
+		.trcd = 3, .trcd_05T = 0,
+		.twr = 6, .twr_05T = 1,
+		.twtr = 4, .twtr_05T = 1,
+		.tpbr2pbr = 7, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 8, .tr2mrw_05T = 1,
+		.tw2mrw = 6, .tw2mrw_05T = 1,
+		.tmrr2mrw = 7, .tmrr2mrw_05T = 0,
+		.tmrw = 3, .tmrw_05T = 0,
+		.tmrd = 3, .tmrd_05T = 0,
+		.tmrwckel = 4, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 4, .tmrri_05T = 0,
+		.trrd = 1, .trrd_05T = 0,
+		.trrd_4266 = 0, .trrd_4266_05T = 1,
+		.tfaw = 0, .tfaw_05T = 0,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 1, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 4, .trtw_odt_on_05T = 0,
+		.txrefcnt = 44,
+		.tzqcs = 12,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 3,
+		.xrtw2r_odt_off = 3,
+		.xrtr2w_odt_on = 3,
+		.xrtr2w_odt_off = 3,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 16,
+		.hwset_mr2_op = 18,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 3, .trcd_derate_05T = 0,
+		.trc_derate = 1, .trc_derate_05T = 0,
+		.tras_derate = 0, .tras_derate_05T = 0,
+		.trpab_derate = 2, .trpab_derate_05T = 0,
+		.trp_derate = 1, .trp_derate_05T = 1,
+		.trrd_derate = 1, .trrd_derate_05T = 0,
+		.trtpd = 7, .trtpd_05T = 1,
+		.twtpd = 8, .twtpd_05T = 1,
+		.tmrr2w_odt_off = 3,
+		.tmrr2w_odt_on = 5,
+		.ckeprd = 1,
+		.ckelckcnt = 2,
+		.zqlat2 = 5,
+		.dqsinctl = 2, .datlat = 9
+	},
+	{
+		.freq_group = DDRFREQ_600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 16, .write_lat =  8, .div_mode =  DIV8_MODE,
+		.tras = 0, .tras_05T = 0,
+		.trp = 1, .trp_05T = 1,
+		.trpab = 2, .trpab_05T = 0,
+		.trc = 0, .trc_05T = 1,
+		.trfc = 30, .trfc_05T = 1,
+		.trfcpb = 9, .trfcpb_05T = 1,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 0, .trtp_05T = 1,
+		.trcd = 3, .trcd_05T = 0,
+		.twr = 6, .twr_05T = 0,
+		.twtr = 4, .twtr_05T = 1,
+		.tpbr2pbr = 7, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 9, .tr2mrw_05T = 0,
+		.tw2mrw = 6, .tw2mrw_05T = 1,
+		.tmrr2mrw = 7, .tmrr2mrw_05T = 1,
+		.tmrw = 3, .tmrw_05T = 0,
+		.tmrd = 3, .tmrd_05T = 0,
+		.tmrwckel = 4, .tmrwckel_05T = 0,
+		.tpde = 1, .tpde_05T = 1,
+		.tpdx = 1, .tpdx_05T = 0,
+		.tmrri = 4, .tmrri_05T = 0,
+		.trrd = 1, .trrd_05T = 0,
+		.trrd_4266 = 0, .trrd_4266_05T = 1,
+		.tfaw = 0, .tfaw_05T = 0,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 2, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 5, .trtw_odt_on_05T = 0,
+		.txrefcnt = 44,
+		.tzqcs = 12,
+		.xrtw2w_new_mode = 4,
+		.xrtw2w_old_mode = 6,
+		.xrtw2r_odt_on = 3,
+		.xrtw2r_odt_off = 2,
+		.xrtr2w_odt_on = 3,
+		.xrtr2w_odt_off = 3,
+		.xrtr2r_new_mode = 3,
+		.xrtr2r_old_mode = 6,
+		.tr2mrr = 4,
+		.vrcgdis_prdcnt = 16,
+		.hwset_mr2_op = 18,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 3, .trcd_derate_05T = 0,
+		.trc_derate = 1, .trc_derate_05T = 0,
+		.tras_derate = 0, .tras_derate_05T = 0,
+		.trpab_derate = 2, .trpab_derate_05T = 0,
+		.trp_derate = 1, .trp_derate_05T = 1,
+		.trrd_derate = 1, .trrd_derate_05T = 0,
+		.trtpd = 8, .trtpd_05T = 0,
+		.twtpd = 9, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 4,
+		.tmrr2w_odt_on = 6,
+		.ckeprd = 1,
+		.ckelckcnt = 2,
+		.zqlat2 = 5,
+		.dqsinctl = 2, .datlat = 9
+	},
+	{
+		.freq_group = DDRFREQ_400, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
+		.read_lat = 14, .write_lat =  8, .div_mode =  DIV4_MODE,
+		.tras = 1, .tras_05T = 0,
+		.trp = 2, .trp_05T = 0,
+		.trpab = 3, .trpab_05T = 0,
+		.trc = 3, .trc_05T = 0,
+		.trfc = 44, .trfc_05T = 0,
+		.trfcpb = 16, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 3, .trtp_05T = 0,
+		.trcd = 4, .trcd_05T = 0,
+		.twr = 12, .twr_05T = 0,
+		.twtr = 10, .twtr_05T = 0,
+		.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 16, .tr2mrw_05T = 0,
+		.tw2mrw = 13, .tw2mrw_05T = 0,
+		.tmrr2mrw = 14, .tmrr2mrw_05T = 0,
+		.tmrw = 6, .tmrw_05T = 0,
+		.tmrd = 6, .tmrd_05T = 0,
+		.tmrwckel = 8, .tmrwckel_05T = 0,
+		.tpde = 3, .tpde_05T = 0,
+		.tpdx = 3, .tpdx_05T = 0,
+		.tmrri = 7, .tmrri_05T = 0,
+		.trrd = 1, .trrd_05T = 0,
+		.trrd_4266 = 1, .trrd_4266_05T = 0,
+		.tfaw = 0, .tfaw_05T = 0,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 6, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 11, .trtw_odt_on_05T = 0,
+		.txrefcnt = 58,
+		.tzqcs = 16,
+		.xrtw2w_new_mode = 9,
+		.xrtw2w_old_mode = 10,
+		.xrtw2r_odt_on = 7,
+		.xrtw2r_odt_off = 5,
+		.xrtr2w_odt_on = 9,
+		.xrtr2w_odt_off = 9,
+		.xrtr2r_new_mode = 6,
+		.xrtr2r_old_mode = 8,
+		.tr2mrr = 8,
+		.vrcgdis_prdcnt = 20,
+		.hwset_mr2_op = 18,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 4, .trcd_derate_05T = 0,
+		.trc_derate = 4, .trc_derate_05T = 0,
+		.tras_derate = 1, .tras_derate_05T = 0,
+		.trpab_derate = 3, .trpab_derate_05T = 0,
+		.trp_derate = 2, .trp_derate_05T = 0,
+		.trrd_derate = 2, .trrd_derate_05T = 0,
+		.trtpd = 15, .trtpd_05T = 0,
+		.twtpd = 15, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 10,
+		.tmrr2w_odt_on = 12,
+		.ckeprd = 2,
+		.ckelckcnt = 3,
+		.zqlat2 = 6,
+		.dqsinctl = 5, .datlat = 15
+	},
+	{
+		.freq_group = DDRFREQ_400, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
+		.read_lat = 16, .write_lat =  8, .div_mode =  DIV4_MODE,
+		.tras = 1, .tras_05T = 0,
+		.trp = 2, .trp_05T = 0,
+		.trpab = 3, .trpab_05T = 0,
+		.trc = 3, .trc_05T = 0,
+		.trfc = 44, .trfc_05T = 0,
+		.trfcpb = 16, .trfcpb_05T = 0,
+		.txp = 0, .txp_05T = 0,
+		.trtp = 3, .trtp_05T = 0,
+		.trcd = 4, .trcd_05T = 0,
+		.twr = 12, .twr_05T = 0,
+		.twtr = 10, .twtr_05T = 0,
+		.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
+		.tpbr2act = 0, .tpbr2act_05T = 0,
+		.tr2mrw = 17, .tr2mrw_05T = 0,
+		.tw2mrw = 13, .tw2mrw_05T = 0,
+		.tmrr2mrw = 15, .tmrr2mrw_05T = 0,
+		.tmrw = 6, .tmrw_05T = 0,
+		.tmrd = 6, .tmrd_05T = 0,
+		.tmrwckel = 8, .tmrwckel_05T = 0,
+		.tpde = 3, .tpde_05T = 0,
+		.tpdx = 3, .tpdx_05T = 0,
+		.tmrri = 7, .tmrri_05T = 0,
+		.trrd = 1, .trrd_05T = 0,
+		.trrd_4266 = 1, .trrd_4266_05T = 0,
+		.tfaw = 0, .tfaw_05T = 0,
+		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
+		.trtw_odt_off = 7, .trtw_odt_off_05T = 0,
+		.trtw_odt_on = 12, .trtw_odt_on_05T = 0,
+		.txrefcnt = 58,
+		.tzqcs = 16,
+		.xrtw2w_new_mode = 9,
+		.xrtw2w_old_mode = 10,
+		.xrtw2r_odt_on = 6,
+		.xrtw2r_odt_off = 4,
+		.xrtr2w_odt_on = 10,
+		.xrtr2w_odt_off = 10,
+		.xrtr2r_new_mode = 6,
+		.xrtr2r_old_mode = 9,
+		.tr2mrr = 8,
+		.vrcgdis_prdcnt = 20,
+		.hwset_mr2_op = 18,
+		.hwset_mr13_op = 24,
+		.hwset_vrcg_op = 16,
+		.trcd_derate = 4, .trcd_derate_05T = 0,
+		.trc_derate = 4, .trc_derate_05T = 0,
+		.tras_derate = 1, .tras_derate_05T = 0,
+		.trpab_derate = 3, .trpab_derate_05T = 0,
+		.trp_derate = 2, .trp_derate_05T = 0,
+		.trrd_derate = 2, .trrd_derate_05T = 0,
+		.trtpd = 16, .trtpd_05T = 0,
+		.twtpd = 15, .twtpd_05T = 0,
+		.tmrr2w_odt_off = 11,
+		.tmrr2w_odt_on = 13,
+		.ckeprd = 2,
+		.ckelckcnt = 3,
+		.zqlat2 = 6,
+		.dqsinctl = 5, .datlat = 15
+	},
+};
+
+#endif  /* __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ */