diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-25 21:07:59 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:09:42 +0200 |
| commit | 4a83f1cf24b793db40606febb8e27cee90452590 (patch) | |
| tree | 74943b190d2aa7c97da72d59f816157d4bc947e9 /src/soc/mediatek | |
| parent | 3c80408fc8aa7b4099493acd7420f8d62ce65a48 (diff) | |
src/soc: Add required space before opening parenthesis '('
Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16324
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 6 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/dramc_pi_calibration_api.c | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/emi.c | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index e3efec9cf8..83ba9995f3 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -99,7 +99,7 @@ static void mem_pll_pre_init(u32 channel) setbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 24 | 0x1 << 7); - if(channel == CHANNEL_A) { + if (channel == CHANNEL_A) { /* select memory clock sync for channel A (internal source) */ clrbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 3); } @@ -292,7 +292,7 @@ static void mem_pll_phase_cali(u32 channel) /* 7. delay line overflow break */ for (i = 0; i < 3; i++) { - if(mempll[i].delay >= 32) { + if (mempll[i].delay >= 32) { die("MEMPLL calibration fail\n"); } } @@ -704,7 +704,7 @@ void dramc_runtime_config(u32 channel, /* if frequency >1600, tCKE should >7 clk */ setbits_le32(&ch[channel].ao_regs->dummy, 0x1 << 4); - if(sdram_params->dram_freq * 2 < 1600 * MHz) + if (sdram_params->dram_freq * 2 < 1600 * MHz) die("set tCKE error in runtime config"); /* DDRPHY C/A and DQ M_CK clock gating enable */ diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 0c68ad9103..e77ec7cb1f 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -79,7 +79,7 @@ void ca_training(u32 channel, const struct mt8173_sdram_params *sdram_params) 0, 1, 3, 3, 3, 4, 4, 5, 5 }; - for(i = 0; i < CATRAINING_NUM; i++) { + for (i = 0; i < CATRAINING_NUM; i++) { ca_shift[i] = params->ca_train[channel][i]; ca_shift_avg8 += ca_shift[i]; } diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index 9c89134932..c021303a4d 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -89,7 +89,7 @@ static void do_calib(const struct mt8173_sdram_params *sdram_params) transfer_to_reg_control(); /* do dram calibration for channel A and B */ - for(channel = 0; channel < CHANNEL_NUM; channel++) { + for (channel = 0; channel < CHANNEL_NUM; channel++) { ca_training(channel, sdram_params); write_leveling(channel, sdram_params); |