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authorJonathan Zhang <jonzhang@fb.com>2020-08-05 20:26:55 -0700
committerAngel Pons <th3fanbus@gmail.com>2020-08-08 20:13:37 +0000
commit7a1ebf9b8f44adaba89c0d95890b64ecd8fc7399 (patch)
tree53e5bd4511fc1ed50d1fa3332842ad4aac50b0d3 /src/soc/mediatek
parentca55343b76cda66d5be1dea9eb2be3fbee901ea7 (diff)
vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc
Intel CPX-SP ww32 release has a number of bug fixes: a. It fixed the issue related to some PCIe ports being hidden. This affected DeltaLake config A, made the onboard PCIe NIC device not working. ww32 release added two UPD parameters: PEXPHIDE, HidePEXPMenu. b. It fixed the regression related to MRC cache. c. It fixed the issue related to VT-d support, and added X2apic UPD paramter. A separate PR will be submitted to enable VT-d in coreboot. d. It fixed the issue related to enabling thermal device with PCI or ACPI mode. [CB:44075] was submitted to enable it in coreboot. e. It fixed the issue of FSP log level change UPD parameter DebugPrintLevel not working. There is a change in IIO UDS Hob. TESTED=booted YV3 config A, and rebooted it. Access the target OS remotely. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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