soc/mediatek/mt8192: Add spi driver

Add driver for MT8192 SPI controller

TEST=Boots correctly on MT8192EVB

Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Change-Id: I2094dd2f14ad19b7dbd66a8e694cc71d654a2b4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

3 files changed, 191 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h
index c4b30472cd..e0cd5364a3 100644
--- a/src/soc/mediatek/mt8192/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h
@@ -23,6 +23,14 @@ enum {
 	APMIXED_BASE		= IO_PHYS + 0x0000C000,
 	PWRAP_BASE		= IO_PHYS + 0x0000D000,
 	UART0_BASE		= IO_PHYS + 0x01002000,
+	SPI0_BASE		= IO_PHYS + 0x0100A000,
+	SPI1_BASE		= IO_PHYS + 0x01010000,
+	SPI2_BASE		= IO_PHYS + 0x01012000,
+	SPI3_BASE		= IO_PHYS + 0x01013000,
+	SPI4_BASE		= IO_PHYS + 0x01018000,
+	SPI5_BASE		= IO_PHYS + 0x01019000,
+	SPI6_BASE		= IO_PHYS + 0x0101D000,
+	SPI7_BASE		= IO_PHYS + 0x0101E000,
 	SSUSB_IPPC_BASE		= IO_PHYS + 0x01203e00,
 	SFLASH_REG_BASE		= IO_PHYS + 0x01234000,
 	IOCFG_RM_BASE		= IO_PHYS + 0x01C20000,
diff --git a/src/soc/mediatek/mt8192/include/soc/spi.h b/src/soc/mediatek/mt8192/include/soc/spi.h
new file mode 100644
index 0000000000..034fa3570a
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/spi.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MTK_MT8192_SPI_H
+#define MTK_MT8192_SPI_H
+
+#include <soc/spi_common.h>
+
+#define SPI_BUS_NUMBER 8
+
+/* SPI peripheral register map. */
+typedef struct mtk_spi_regs {
+	uint32_t spi_cfg0_reg;
+	uint32_t spi_cfg1_reg;
+	uint32_t spi_tx_src_reg;
+	uint32_t spi_rx_dst_reg;
+	uint32_t spi_tx_data_reg;
+	uint32_t spi_rx_data_reg;
+	uint32_t spi_cmd_reg;
+	uint32_t spi_status0_reg;
+	uint32_t spi_status1_reg;
+	uint32_t spi_pad_macro_sel_reg;
+	uint32_t spi_cfg2_reg;
+	uint32_t spi_tx_src_64_reg;
+	uint32_t spi_rx_dst_64_reg;
+} mtk_spi_regs;
+
+check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24);
+
+enum {
+	SPI_CFG0_CS_HOLD_SHIFT = 0,
+	SPI_CFG0_CS_SETUP_SHIFT = 16,
+};
+
+enum {
+	SPI_CFG2_SCK_LOW_SHIFT = 0,
+	SPI_CFG2_SCK_HIGH_SHIFT = 16,
+};
+
+enum {
+	SPI_CFG1_TICK_DLY_SHIFT = 29,
+	SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT,
+};
+
+#endif
diff --git a/src/soc/mediatek/mt8192/spi.c b/src/soc/mediatek/mt8192/spi.c
new file mode 100644
index 0000000000..577536a9f7
--- /dev/null
+++ b/src/soc/mediatek/mt8192/spi.c
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <assert.h>
+#include <soc/addressmap.h>
+#include <soc/gpio.h>
+#include <soc/spi.h>
+
+struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = {
+	{
+		.regs = (void *)SPI0_BASE,
+		.cs_gpio = GPIO(SPI0_CSB),
+	},
+	{
+		.regs = (void *)SPI1_BASE,
+		.cs_gpio = GPIO(SPI1_CSB),
+	},
+	{
+		.regs = (void *)SPI2_BASE,
+		.cs_gpio = GPIO(SCP_SPI2_CSB),
+	},
+	{
+		.regs = (void *)SPI3_BASE,
+		.cs_gpio = GPIO(CAM_RST1),
+	},
+	{
+		.regs = (void *)SPI4_BASE,
+		.cs_gpio = GPIO(EINT5),
+	},
+	{
+		.regs = (void *)SPI5_BASE,
+		.cs_gpio = GPIO(SPI5_CSB),
+	},
+	{
+		.regs = (void *)SPI6_BASE,
+		.cs_gpio = GPIO(EINT1),
+	},
+	{
+		.regs = (void *)SPI7_BASE,
+		.cs_gpio = GPIO(SDA0),
+	}
+};
+
+struct pad_func {
+	u8 pin_id;
+	u8 func;
+};
+
+#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func}
+#define PAD_FUNC_GPIO(name) {PAD_##name##_ID, 0}
+
+static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = {
+	{
+		PAD_FUNC(SPI0_MI, SPI0_A_MI),
+		PAD_FUNC_GPIO(SPI0_CSB),
+		PAD_FUNC(SPI0_MO, SPI0_A_MO),
+		PAD_FUNC(SPI0_CLK, SPI0_A_CLK),
+	},
+	{
+		PAD_FUNC(SPI1_MI, SPI1_A_MI),
+		PAD_FUNC_GPIO(SPI1_CSB),
+		PAD_FUNC(SPI1_MO, SPI1_A_MO),
+		PAD_FUNC(SPI1_CLK, SPI1_A_CLK),
+	},
+	{
+		PAD_FUNC(SCP_SPI2_MI, SPI2_MI),
+		PAD_FUNC_GPIO(SCP_SPI2_CSB),
+		PAD_FUNC(SCP_SPI2_MO, SPI2_MO),
+		PAD_FUNC(SCP_SPI2_CK, SPI2_CLK),
+	},
+	{
+		PAD_FUNC(CAM_RST2, SPI3_MI),
+		PAD_FUNC_GPIO(CAM_RST1),
+		PAD_FUNC(CAM_PDN0, SPI3_MO),
+		PAD_FUNC(CAM_RST0, SPI3_CLK),
+	},
+	{
+		PAD_FUNC(EINT6, SPI4_A_MI),
+		PAD_FUNC_GPIO(EINT5),
+		PAD_FUNC(EINT7, SPI4_A_MO),
+		PAD_FUNC(EINT4, SPI4_A_CLK),
+	},
+	{
+		PAD_FUNC(SPI5_MI, SPI5_A_MI),
+		PAD_FUNC_GPIO(SPI5_CSB),
+		PAD_FUNC(SPI5_MO, SPI5_A_MO),
+		PAD_FUNC(SPI5_CLK, SPI5_A_CLK),
+	},
+	{
+		PAD_FUNC(EINT2, SPI6_MI),
+		PAD_FUNC_GPIO(EINT1),
+		PAD_FUNC(EINT3, SPI6_MO),
+		PAD_FUNC(EINT0, SPI6_CLK),
+	},
+	{
+		PAD_FUNC(EINT16, SPI7_A_MI),
+		PAD_FUNC_GPIO(SDA0),
+		PAD_FUNC(EINT17, SPI7_A_MO),
+		PAD_FUNC(SCL0, SPI7_A_CLK),
+	}
+};
+
+void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select)
+{
+	assert(bus < SPI_BUS_NUMBER);
+	assert(pad_select == SPI_PAD0_MASK);
+	const struct pad_func *ptr = NULL;
+
+	ptr = pad0_funcs[bus];
+	for (int i = 0; i < 4; i++)
+		gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func);
+}
+
+void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
+			unsigned int tick_dly)
+{
+	write32(&regs->spi_cfg0_reg,
+		((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) |
+		((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT));
+
+	write32(&regs->spi_cfg2_reg,
+		((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) |
+		((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT));
+
+	clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK |
+		     SPI_CFG1_CS_IDLE_MASK,
+		     (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
+		     ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
+}
+
+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+	{
+		.ctrlr = &spi_ctrlr,
+		.bus_start = 0,
+		.bus_end = SPI_BUS_NUMBER - 1,
+	},
+};
+
+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);