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authorTeddy Shih <teddyshih@ami.corp-partner.google.com>2022-06-24 16:13:00 +0800
committerKarthik Ramasubramanian <kramasub@google.com>2022-08-03 14:00:53 +0000
commit433810a5777cbfb1ee5cae5b284481acdbf63048 (patch)
treeaf21538cff0795a8bf853b2cba3ee8a08cc2319b /src/soc/mediatek
parent4c7ee500721f15130f7cb5c4355740dd7375b705 (diff)
mb/google/dedede/var/beadrix: Update SoC gpio pin of DMIC
Update SoC GPIO setting of unused DMIC channel according to beadrix schematics. GPP_S2 : NF2 -> NC (DMIC1_CLK) GPP_S3 : NF2 -> NC (DMIC1_DATA) BUG=b:203113413, b:237224862 BRANCH=None TEST=on beadrix, validated by beadrix's DMIC working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ibe2f432cd74b546218ff4ee6e428e9eed9ac611f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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